Victim cache with dynamic allocation of entries

1. A caching system comprising:

a first sub-cache; and

a second sub-cache coupled in parallel with the first sub-cache, wherein:

the second sub-cache includes a set of lines and a set of line type bits;

each line of the set of lines is configured to operate in a first manner to store a respective set of data associated with a write-miss and operate in a second manner to store a respective set of data associated with an eviction of a cache entry from the first sub-cache; and

each line type bit of the set of line type bits is configured to store a first indication based on that a respective set of data of a respective line of the set of lines is associated with a write-miss and a second indication based on that the respective set of data is associated with an eviction of a cache entry from the first sub-cache.

2. The caching system of claim 1 , wherein the second sub-cache further comprises a tag random access memory (RAM) configured to store a respective memory address for each line of a first subset of the set of lines associated with a write-miss.

3. The caching system of claim 1 , wherein the second sub-cache further comprises a byte-enable memory configured to store a respective byte-enable mask for each line of the set of lines associated with a write-miss.

4. The caching system of claim 3 , wherein the byte-enable memory includes memory positions corresponding with each line of the set of lines of the second sub-cache.

5. The caching system of claim 1 , wherein the set of line type bits is stored in a memory tracking modified, exclusive, shared, and invalid (MESI) states of the set of lines in the second sub-cache.

6. The caching system of claim 1 , wherein the first sub-cache is a n-way set associative cache and wherein the second sub-cache is a fully associative cache.

7. The caching system of claim 1 , wherein the write-miss is associated with a miss in the first sub-cache and a miss in the second sub-cache.

8. The caching system of claim 1 , wherein the caching system is configured to:

receive a write request; and

determine whether the write request is associated with a miss in the first sub-cache and, in parallel, determine whether the write request is associated with a miss in the second sub-cache.

9. A method for caching data, comprising:

receiving, by a caching system, a write memory request for a memory address;

determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache;

determining, by a second sub-cache of the caching system, the second sub-cache coupled in parallel with the first sub-cache, that the memory address is not cached in the second sub-cache;

storing a first set of data associated with the write memory request in a first line of the second sub-cache;

storing, in a first line type bit of the second sub-cache, a first indication that the first set of data is associated with a write-miss;

storing, in the first line of the second sub-cache, a second set of data associated with an eviction from the first sub-cache; and

storing, in the first line type bit of the second sub-cache, a second indication that the second set of data is associated with an eviction from the first sub-cache.

10. The method of claim 9 , further comprising storing a memory address associated with the first set of data in a tag random access memory (RAM).

11. The method of claim 9 , further comprising storing byte enable logic associated with the first set of data in a byte-enable memory.

12. The method of claim 9 , wherein the first line type bit is stored in a memory tracking modified, exclusive, shared, and invalid (MESI) states of entries in the second sub-cache.

13. The method of claim 9 , further comprising:

evicting a cache entry from a line of the second sub-cache, and wherein the storing of the first set of data associated with the write memory request comprises storing the first set of data in the line.

14. A device comprising:

a processor;

a first sub-cache; and

a second sub-cache coupled in parallel with the first sub-cache, wherein:

the second sub-cache includes a set of lines each configured to operate in a first manner to store write-miss data and to operate in a second manner to store data evicted from the first sub-cache; and

the second sub-cache includes a first line type bit configured to store a first indication based on that a first line of the set of lines is associated with a write miss and a second indication based on that the first line is associated with an eviction from the first sub-cache.

15. The device of claim 14 , wherein the second sub-cache further comprises a tag random access memory (RAM) configured to store a memory address associated with the first line when the first line is associated with the write miss.

16. The device of claim 14 , wherein the second sub-cache further comprises a byte-enable memory configured to store a byte-enable mask associated with the first line when the first line is associated with the write miss.

17. The device of claim 16 , wherein the byte-enable memory includes memory positions corresponding with each line of the set of lines of the second sub-cache.

18. The device of claim 14 , wherein the first line type bit is stored in a memory tracking modified, exclusive, shared, and invalid (MESI) states of the set of lines of the second sub-cache.

19. The device of claim 14 , wherein the first sub-cache is a n-way set associative cache and wherein the second sub-cache is a fully associative cache.