Memory device, memory module including the memory device, and operating method of memory controller

1. A memory device, comprising:

a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored;

an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit,

wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected;

a plurality of pins connected to the memory controller; and

a command decoder configured to separately receive a normal read command and the uncorrected read command based on at least one of the plurality of pins,

wherein the normal read command is configured to correct the error bit in the first data,

wherein the ECC engine is further configured to generate corrected data by correcting the error bit and output the second data instead of the corrected data, in response to receiving a control signal based on the uncorrected read command from the command decoder.

2. The memory device of claim 1 , wherein the at least one of the plurality of pins comprises a command/address (CA) pin.

3. The memory device of claim 1 , wherein the first data comprises 128 bits, and the parity bit comprises 8 bits.

4. The memory device of claim 3 , wherein the ECC engine is further configured to generate corrected data obtained by correcting the error bit, in response to the normal read command.

5. The memory device of claim 3 , wherein a burst length of the memory device is 16,

the plurality of pins comprise eight data input/output pins,

the first data is divided into four units of data based on the data input/output pins and the burst length,

the error bit is one of first and second error bits in any one unit of data of the four units of data, and

the ECC engine miscorrects the first and second error bits in response to the normal read command.

6. The memory device of claim 1 , wherein the ECC engine is further configured to bypass an error correction operation on the first data and directly output the second data, in response to receiving a control signal based on the uncorrected read command from the command decoder.

7. The memory device of claim 1 , further comprising:

a volatile memory device.

8. The memory device of claim 7 , wherein the volatile memory device operates at 4 bits (×4) or 8 bits (×8).

9. A memory device, comprising:

a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored;

an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit,

wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected;

a plurality of pins connected to the memory controller; and

a command decoder configured to separately receive a normal read command and the uncorrected read command based on at least one of the plurality of pins,

wherein the normal read command is configured to correct the error bit in the first data,

wherein the at least one of the plurality of pins comprises a don't care pin of the normal read command.

10. A memory device, comprising:

a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored;

an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit,

wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected;

a plurality of pins connected to the memory controller; and

a command decoder configured to separately receive a normal read command and the uncorrected read command based on at least one of the plurality of pins,

wherein the normal read command is configured to correct the error bit in the first data,

wherein the ECC engine comprises a syndrome generator configured to calculate syndrome data based on the first data and the parity bit, and

the syndrome generator is further configured to always output the syndrome data as a first value, in response to receiving a control signal based on the uncorrected read command from the command decoder.

11. The memory device of claim 10 , wherein the first value comprises zero.

12. A memory device, comprising:

a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored; and

an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit,

wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected,

wherein the ECC engine is further configured to:

receive a plurality of uncorrected read commands from the memory controller at a first cycle interval,

wherein the uncorrected read command is one of the plurality of uncorrected read commands;

output the first data stored in the normal region, in response to each of the plurality of uncorrected read commands; and

read all of the first data stored in the normal region within a first period, in response to the plurality of uncorrected read commands.