Self-aligning backside contact process and devices thereof
A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.
1. A method, comprising:
forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate, the source/drain feature and the semiconductor layer stack disposed along a first plane that extends in a first direction in a top down view;
forming a dummy fin disposed along a second plane in the top view, the second plane parallel to the first plane and extending in the first direction, wherein the dummy fin is adjacent to each of the source/drain feature and the semiconductor layer stack in a second direction in the top down view, the second direction perpendicular to the first direction;
performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, wherein the first trench extends from the dummy fin to the source/drain feature;
forming a first dielectric layer in the first trench; and
replacing a second portion of the dummy fin with a source/drain contact.
2. The method of claim 1 , further comprising:
forming a dummy gate stack over the dummy fin and the semiconductor layer stack and adjacent to the source/drain feature; and
forming an interlayer dielectric over the dummy fin, the dummy gate stack, and the source/drain feature.
3. The method of claim 1 , wherein the dummy fin includes silicon.
4. The method of claim 1 , further comprising:
before forming the dummy fin, forming a shallow trench isolation layer along a bottom and sidewalls of the first trench; and
forming a cladding layer over the shallow trench isolation layer and on sidewalls of the first trench.
5. The method of claim 1 , further comprising:
before the replacing the second portion of the dummy fin with the source/drain contact, removing a third portion of the dummy fin thereby forming a second trench, wherein the third portion of the dummy fin is below a dummy gate stack; and
forming a second dielectric layer in the second trench.
6. The method of claim 5 , wherein the replacing the second portion of the dummy fin with the source/drain contact further comprises:
etching the second portion of the dummy fin from the backside of the substrate, exposing a sidewall surface of the source/drain feature;
forming a silicide layer over the exposed sidewall surface of the source/drain feature; and
depositing the source/drain contact over the silicide layer.
7. The method of claim 1 , further comprising:
forming a power rail over a portion of the source/drain contact exposed on the backside of the substrate.
8. A method, comprising:
forming a first semiconductor fin over a substrate, the first semiconductor fin extending in a first direction in a top view;
forming a second semiconductor fin over the substrate, the second semiconductor fin parallel to the first semiconductor fin and extending in the first direction in the top view;
depositing a dummy fin adjacent to the first semiconductor fin and adjacent to the second semiconductor fin, wherein each of the first and second semiconductor fins are disposed laterally from the dummy fin along a second direction perpendicular to the first direction;
etching a first portion of the dummy fin from a backside of the substrate thereby forming a first trench, wherein the first trench extends from the first semiconductor fin to the second semiconductor fin;
depositing a dielectric layer in the first trench;
etching a second portion of the dummy fin from the backside of the substrate thereby forming a second trench; and
depositing a metal layer in the second trench.
9. The method of claim 8 , further comprising:
forming a power rail over a portion of the metal layer exposed on the backside of the substrate.
10. The method of claim 8 , further comprising:
before depositing the dummy fin, depositing a shallow trench isolation feature over the substrate, the shallow trench isolation feature extending from the first semiconductor fin to the second semiconductor fin;
depositing a cladding layer over the shallow trench isolation feature and along a first sidewall of the first semiconductor fin and along a second sidewall of the second semiconductor fin, the second sidewall opposing the first sidewall; and
wherein the dummy fin extends from the first sidewall to the second sidewall.
11. The method of claim 8 , further comprising:
forming a dummy gate stack over the first semiconductor fin, the second semiconductor fin, and the dummy fin; and
forming an interlayer dielectric over the dummy gate stack, the first semiconductor fin, the second semiconductor fin, and the dummy fin.
12. The method of claim 8 , further comprising:
forming a source/drain feature in the first semiconductor fin, wherein the source/drain feature contacts the metal layer.
13. The method of claim 8 , wherein the dummy fin includes silicon.
14. The method of claim 8 , further comprising:
wherein the etching the second portion of the dummy fin exposes a sidewall surface of a source/drain feature;
forming a silicide layer over the exposed sidewall surface of the source/drain feature; and
wherein the metal layer is further formed over the silicide layer.
15. A method, comprising:
epitaxially growing a source/drain feature in contact with a plurality of semiconductor channel layers along a first side of the source/drain feature, the first side of the source/drain feature facing a first direction in a top down view;
forming a dummy fin adjacent to and interfacing the source/drain feature along a second side of the source/drain feature, the second side of the source/drain feature facing a second direction perpendicular to the first direction in the top down view;
replacing a first portion of the dummy fin with a first dielectric layer; and
replacing a second portion of the dummy fin with a source/drain contact, the source/drain contact interposing the first dielectric layer and the source/drain feature, and the source/drain contact electrically connected to the source/drain feature.
16. The method of claim 15 , wherein the replacing the first portion of the dummy fin comprises:
performing an etching process from a backside of a substrate to remove the first portion of the dummy fin and form a first trench; and
forming the first dielectric layer in the first trench.
17. The method of claim 15 , further comprising:
forming a dummy gate stack over the dummy fin and adjacent to the source/drain feature; and
forming an interlayer dielectric over the dummy fin, the dummy gate stack, and the source/drain feature.
18. The method of claim 15 , wherein the dummy fin includes a second dielectric layer different than the first dielectric layer.
19. The method of claim 15 , further comprising:
forming a backside power rail electrically connected to the source/drain contact.
20. The method of claim 15 , wherein the replacing the second portion of the dummy fin with the source/drain contact further comprises:
etching the second portion of the dummy fin from a backside of a substrate to form a second trench that exposes a sidewall surface of the source/drain feature;
forming a silicide layer within the second trench and over the exposed sidewall surface of the source/drain feature; and
forming the source/drain contact over the silicide layer.