IP Library › Granted Patent US 12,144,170
Granted Patent B2
US 12,144,170 · App. 18/424,190 · Granted Nov 12, 2024

Semiconductor device and manufacturing method of semiconductor device

Inventor: Nam Jae Lee (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B41/35H10B41/10H10B41/20H10B43/10H10B43/20H10B43/35
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Quick Facts
Patent No.
US 12,144,170
App. No.
18/424,190
Granted
Nov 12, 2024
Kind
B2
Abstract

A semiconductor device includes a stacked body including a conductive pattern and an insulating pattern, a cell plug passing through the stacked body, a semiconductor layer, a peripheral transistor arranged on the semiconductor layer, a first conductor coupling the peripheral transistor to the cell plug, a second conductor coupled to the conductive pattern, a pass plug coupled to the second conductor, and a pass gate surrounding the pass plug, wherein the pass gate is arranged at substantially a same level as the semiconductor layer.

Claims (27)

1. A method of manufacturing a semiconductor device, comprising:

forming a stacked body including a conductive pattern and an insulating pattern;

forming a cell plug passing through the stacked body;

forming a substrate including a first region and a second region on the first region;

forming a pass plug surrounded by the substrate;

electrically connecting the pass plug to the conductive pattern;

removing the first region of the substrate to expose a portion of the pass plug; and

forming a contact coupled to the portion of the pass plug.

2. The method of claim 1 , wherein electrically connecting the pass plug to the conductive pattern comprises bonding a first bonding pad coupled to the pass plug and a second bonding pad coupled to the conductive pattern.

3. The method of claim 1 , further comprising forming a peripheral transistor on the substrate.

4. The method of claim 3 , further comprising electrically connecting the peripheral transistor to the cell plug.

5. The method of claim 4 , wherein the peripheral transistor is electrically connected to the cell plug, when the pass plug is electrically connected to the conductive pattern.

6. The method of claim 1 , further comprising forming a separating structure passing through the second region of the substrate.

7. The method of claim 6 , wherein forming the separating structure comprises:

forming a trench passing through the second region of the substrate;

conformally forming a first material layer and a second material layer in the trench; and

removing an upper portion of the first material layer and an upper portion of the second material layer.

8. The method of claim 1 , wherein forming the pass plug comprises:

forming a hole passing through the second region of the substrate;

conformally forming a first material layer and a second material layer in the hole; and

removing an upper portion of the first material layer and an upper portion of the second material layer.

9. The method of claim 8 , wherein forming the pass plug further comprises doping the second material layer with impurities.

10. The method of claim 1 , wherein:

the pass plug includes a first pass layer and a second pass layer surrounding the first pass layer, and

forming the contact comprises:

forming a hole passing through the second pass layer; and

forming the contact in the hole.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2024
From: LEE, NAM JAE
To: SK HYNIX INC.
Reel/Frame 066266/0030 →
Priority Claims (1)
KR 10-2020-0146321 · Nov 4, 2020 · national
Continuity (2)
Division 17307756 · May 4, 2021
Related Publication 20240172435A1 · May 23, 2024
Cited By (1)
US 12,438,127