Variable-resistance memory device

1. A variable-resistance memory device comprising:

a substrate having an active region;

a gate structure disposed in the active region;

a drain region disposed on a first side adjacent to the gate structure;

a source region disposed on a second side adjacent to the gate structure;

an interlayer insulating layer covering the active region and having a first contact hole and a second contact hole respectively connected to the drain region and the source region;

a first contact structure filling a lower region of the first contact hole;

a second contact structure filling the second contact hole;

a first electrode layer having a first portion disposed on the first contact structure and having a second portion extending to a sidewall of an upper region of the first contact hole;

a variable-resistance layer disposed on the first electrode layer in the upper region of the first contact hole;

a sidewall spacer disposed between the second portion of the first electrode layer and the variable-resistance layer in the upper region of the first contact hole; and

a second electrode layer disposed on the variable-resistance layer in the upper region of the first contact hole.

2. The variable-resistance memory device of claim 1 , further comprising:

a first interconnection line and a second interconnection line disposed on the interlayer insulating layer, and respectively connected to the second electrode layer and the second contact structure.

3. The variable-resistance memory device of claim 1 , wherein the sidewall spacer extends on a portion of the interlayer insulating layer surrounding the upper region of the first contact hole.

4. The variable-resistance memory device of claim 3 , wherein the sidewall spacer has an upper end disposed to be lower than an upper surface of the interlayer insulating layer.

5. The variable-resistance memory device of claim 4 , wherein the variable-resistance layer extends to the portion of the interlayer insulating layer along the sidewall spacer.

6. The variable-resistance memory device of claim 1 , wherein a region adjacent to an upper end of the sidewall spacer has a width smaller than a width of another region of the sidewall spacer.

7. The variable-resistance memory device of claim 1 , wherein the second electrode layer has an upper surface substantially coplanar with an upper surface of the interlayer insulating layer.

8. The variable-resistance memory device of claim 7 , wherein an upper end of the variable-resistance layer has a surface substantially coplanar with the upper surface of the interlayer insulating layer.

9. The variable-resistance memory device of claim 1 , further comprising:

an oxygen reservoir layer disposed between the variable-resistance layer and the second electrode layer.

10. The variable-resistance memory device of claim 9 , wherein:

the variable-resistance layer includes a compound of metal and oxygen,

the oxygen reservoir layer includes an oxide of the same metal as the metal of the variable-resistance layer, and has an oxygen concentration lower than an oxygen concentration of the variable-resistance layer.

11. The variable-resistance memory device of claim 1 , wherein the first contact structure has an upper surface disposed on a level lower than a level of an upper surface of the second contact structure.

12. The variable-resistance memory device of claim 1 , wherein each of the first and the second contact structures includes a conductive barrier layer and a contact plug.

13. The variable-resistance memory device of claim 12 , wherein the conductive barrier layer of the first contact structure has an upper end disposed to be higher than an upper surface of the first contact structure.

14. The variable-resistance memory device of claim 13 , wherein the conductive barrier layer has a portion disposed between the interlayer insulating layer and the second portion of the first electrode layer.

15. The variable-resistance memory device of claim 13 , wherein the upper end of the conductive barrier layer has substantially the same height as an upper end of the second portion of the first electrode layer.

16. A variable-resistance memory device comprising:

a substrate;

an insulating layer disposed on the substrate and having a contact hole;

a contact structure filling a lower region of the contact hole;

a first electrode layer having a first portion disposed on the contact structure and a second portion extending to a side wall of an upper region of the contact hole;

a variable-resistance layer covering the first electrode layer in the upper region of the contact hole;

a sidewall spacer disposed between the second portion of the first electrode layer and the variable-resistance layer in the upper region of the contact hole; and

a second electrode layer disposed on the variable-resistance layer in the upper region of the first contact hole.

17. The variable-resistance memory device of claim 16 , wherein the sidewall spacer extends onto a portion surrounding the upper region of the contact hole and has an upper end disposed to be lower than an upper surface of the insulating layer.

18. The variable-resistance memory device of claim 16 , wherein the second electrode layer and the variable-resistance layer have surfaces substantially coplanar with an upper surface of the insulating layer.

19. The variable-resistance memory device of claim 16 , wherein:

the contact structure includes a conductive barrier layer and a contact plug, and

the conductive barrier layer has an upper end disposed to be higher than an upper surface of the contact structure.

20. A variable-resistance memory device comprising:

a substrate having an active region;

a gate structure disposed in the active region and extending in one direction;

source/drain regions disposed in the active region on opposite sides of the gate structure;

an interlayer insulating layer covering the active region and having a first contact hole and a second contact hole respectively connected to the source/drain regions;

a first contact structure filling a lower region of the first contact hole;

a second contact structure filling the second contact hole; and

a variable-resistance structure filling the upper region of the first contact hole and having an upper surface substantially coplanar with an upper surface of the interlayer insulating layer,

wherein the variable-resistance structure includes a first electrode layer disposed on the first contact structure and having an extension portion extending to a sidewall of the upper region of the first contact hole, a variable-resistance layer disposed on the first electrode layer, a sidewall spacer disposed between the extension portion of the first electrode layer and the variable-resistance layer, and a second electrode layer disposed on the variable-resistance layer, and

wherein the second electrode layer and the variable-resistance layer are exposed to the upper surface of the variable-resistance structure.