IP Library › Granted Patent US 12,146,237
Granted Patent B2
US 12,146,237 · App. 17/285,827 · Granted Nov 19, 2024

Method of obtaining a smooth surface with epitaxial lateral overgrowth

Inventors: Takeshi Kamikawa (Kyoto, JP); Srinivas Gandrothula (Santa Barbara, CA)
Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
C30B25/04C30B25/18C30B29/403C30B29/406H01L21/02389H01L21/0242H01L21/0254H01L21/02647H01L21/7806H01L29/0657H01L29/2003H01L33/007H01L33/24H01L33/32H01S5/0202H01S5/22H01S5/34333H01S2304/12
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Quick Facts
Patent No.
US 12,146,237
App. No.
17/285,827
Granted
Nov 19, 2024
Kind
B2
Abstract

A method for obtaining a smooth surface of an epi-layer with epitaxial lateral overgrowth. The method does not use mis-cut orientations and does not suppress the occurrence of pyramidal hillocks, but instead embeds the pyramidal hillocks in the epi-layer. A growth restrict mask is used to limit the expansion of the pyramidal hillocks in a lateral direction. The surface of the epi-layer becomes extremely smooth due to the disappearance of the pyramidal hillocks.

Claims (30)

1. A device, comprising:

a plurality of III-nitride semiconductor layers, wherein:

at least one of the plurality of III-nitride semiconductor layers is grown from an opening area in a growth restrict mask, on or above a substrate, and on top of the growth restrict mask, using epitaxial lateral overgrowth,

the at least one of the plurality of III-nitride semiconductor layers contains at least one pyramidal hillock embedded therein,

the pyramidal hillock is formed within the opening area of the growth restrict mask during the epitaxial lateral overgrowth of the at least one of the plurality of III-nitride based semiconductor layers,

the epitaxial lateral overgrowth proceeds until the at least one of the plurality of III-nitride semiconductor layers completely embeds the pyramidal hillock to create a smooth epi-layer surface,

the at least one of the plurality of III-nitride semiconductor layers from adjacent opening areas do not coalesce on top of the growth restrict mask during the epitaxial lateral overgrowth,

the at least one of the plurality of III-nitride semiconductor layers has one or more flat surface regions and bending regions at the edges thereof, and

one or more III-nitride semiconductor device layers are grown on or above the flat surface regions.

2. The device of claim 1 , wherein the growth restrict mask limits expansion of the pyramidal hillock in a lateral direction.

3. The device of claim 1 , wherein the plurality of III-nitride semiconductor layers are grown on or above a III-nitride substrate.

4. The device of claim 1 , wherein the plurality of III-nitride semiconductor layers are grown on or above a hetero-substrate, and a III-nitride template is deposited on or above the hetero-substrate before the plurality of III-nitride semiconductor layers.

5. The device of claim 1 , wherein the plurality of III-nitride semiconductor layers are removed from the III-nitride substrate.

6. A method, comprising:

fabricating a device comprised of a plurality of III-nitride semiconductor layers, wherein:

at least one of the plurality of III-nitride semiconductor layers is grown from an opening area in a growth restrict mask, on or above a substrate, and on top of the growth restrict mask, using epitaxial lateral overgrowth,

at least one of the plurality of III-nitride semiconductor layers contains at least one pyramidal hillock embedded therein,

the pyramidal hillock is formed within the opening area of the growth restrict mask during the epitaxial lateral overgrowth of the at least one of the plurality of III-nitride semiconductor layers,

the epitaxial lateral overgrowth proceeds until the at least one of the plurality of III-nitride semiconductor layers completely embeds the pyramidal hillock to create a smooth epi-layer surface,

the at least one of the plurality of III-nitride semiconductor layers from adjacent opening areas do not coalesce on top of the growth restrict mask during the epitaxial lateral overgrowth,

the at least one of the plurality of III-nitride semiconductor layers has one or more flat surface regions and bending regions at the edges thereof, and

one or more III-nitride semiconductor device layers are grown on or above the flat surface regions.

7. The method of claim 6 , wherein the growth restrict mask limits expansion of the pyramidal hillock in a lateral direction.

8. The method of claim 6 , wherein the plurality of III-nitride semiconductor layers are grown on or above a hetero-substrate, and a III-nitride template is deposited on or above the hetero-substrate before the plurality of III-nitride semiconductor layers.

9. The method of claim 6 , wherein the plurality of III-nitride semiconductor layers are removed from the III-nitride substrate.

10. The method of claim 9 , wherein the plurality of III-nitride semiconductor layers are removed from the III-nitride substrate by:

applying a film to the III-nitride semiconductor layers;

applying a pressure on the film;

changing a temperature of the film and the substrate; and

peeling the film with the III-nitride semiconductor layers from the substrate, after the pressure is applied and the temperature is changed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: KAMIKAWA, TAKESHI; GANDROTHULA, SRINIVAS
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 068874/0715 →
Continuity (2)
Provisional Application 62753225 · Oct 31, 2018
Related Publication 20210381124A1 · Dec 9, 2021