Leveraging processing in memory registers as victim buffers
In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on the address of the row being included in the victim address table.
1. A computing device comprising:
a memory;
a processing in memory circuit having registers for data storage; and
a memory controller having a victim address table configured to include at least one address of at least one row of the memory that is stored in the registers, the memory controller configured to:
receive a request to access a row of the memory; and
access data of the row from the registers based on an address of the row being included in the victim address table.
2. The computing device of claim 1 , wherein an additional row of the memory is open when the request is received, the additional row remaining open after the data of the row is accessed from the registers.
3. The computing device of claim 1 , wherein the memory controller is configured to:
receive a prior request to access the row of the memory before the address of the row is stored in the victim address table; and
responsive to the prior request being received:
open the row of the memory;
access the data of the row from the memory;
load the data of the row into the registers; and
update the victim address table to include the address of the row.
4. The computing device of claim 3 , wherein the memory controller is configured to load the data of the row into the registers and access the data of the row from the memory in parallel.
5. The computing device of claim 3 , wherein the memory controller is configured to load the data of the row into the registers after the data is accessed from the memory.
6. The computing device of claim 3 , wherein the data of the row that is loaded into the registers corresponds to a first portion of the data of the row, and the request is to access the first portion of the data of the row and a second portion of the data of the row.
7. The computing device of claim 6 , wherein the memory controller is configured to automatically close the row after the data of the row is accessed from the memory.
8. The computing device of claim 7 , wherein the memory controller is configured to, in response to the request being received, re-open the row of the memory and access the first portion of the data of the row from the registers in parallel.
9. The computing device of claim 3 , wherein the memory controller is configured to load the data of the row into the registers based on a non-processing in memory workload being serviced.
10. The computing device of claim 3 , wherein the memory controller is configured to load the data of the row into the registers based on an access frequency of the row exceeding a threshold frequency.
11. The computing device of claim 3 , wherein the memory controller is configured to load the data of the row into the registers based on the request being included in a pending request queue.
12. The computing device of claim 3 , wherein the memory controller is configured to update the victim address table to include an indication of a particular register into which the data of the row is loaded, the row being accessed from the particular register in response to the request being received.
13. A method comprising:
receiving, by a memory controller, a request to access a row of a memory;
loading, by the memory controller, data of the row into registers of a processing in memory circuit;
updating, by the memory controller, a victim address table to include an address of the row;
receiving, by the memory controller, a subsequent request to access the row of the memory; and
in response to receiving the subsequent request, accessing, by the memory controller, the data of the row from the registers.
14. The method of claim 13 , wherein the data of the row is accessed from the registers based on the address of the row being included in the victim address table.
15. The method of claim 13 , further comprising, in response to receiving the request:
opening, by the memory controller, the row of the memory; and
accessing, by the memory controller, the data of the row from the memory.
16. The method of claim 15 , further comprising automatically closing, by the memory controller, the row of the memory after the data of the row is accessed from the memory, the row remaining closed after the data of the row is accessed from the registers.
17. The method of claim 15 , wherein the accessing the data of the row from the memory and the loading the data of the row into the registers are performed in parallel.
18. The method of claim 15 , wherein the loading the data of the row into the registers is performed after the accessing the data of the row from the memory.
19. An apparatus comprising:
a memory;
a processing in memory circuit having registers for data storage;
a memory controller having a victim address table configured to include at least one address of at least one row of the memory that is stored in the registers; and
a core to transmit requests to the memory controller, the requests causing the memory controller to:
responsive to a first request to access a row of the memory:
open the row;
access data of the row from the memory;
load the data of the row into the registers; and
update the victim address table to include an address of the row; and
responsive to a second request to access the row, access the data of the row from the registers based on the address of the row being included in the victim address table.
20. The apparatus of claim 19 , wherein the first request causes the memory controller to load the data of the row into the registers based on a non-processing in memory workload being serviced.