Asynchronous communication protocol compatible with synchronous DDR protocol

1. A device comprising:

a non-volatile memory; and

an asynchronous memory interface to interface with a memory controller,

wherein the asynchronous memory interface uses memory channel that is operable for synchronous data communication between the memory controller and the device to send a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller.

2. The device of claim 1 , further comprising a volatile memory, wherein the asynchronous memory interface uses the memory channel to synchronously or asynchronously send the data to the memory controller.

3. The device of claim 2 , wherein the non-volatile memory and the volatile memory are associated with the memory channel.

4. The device of claim 1 , wherein the memory controller synchronously sends data requested by the data access request using the memory channel based on the status of the device.

5. The device of claim 1 , wherein the device feedback indicates that the data requested by the data access request from the memory controller is associated with a data buffer of the non-volatile memory or associated with a volatile memory included in the device.

6. The device of claim 1 , wherein the device includes a memory and the feedback includes address select information of the memory.

7. The device of claim 1 , wherein the memory channel includes physical connections that are used by a dual in-line memory module (DIMM).

8. The device of claim 7 , wherein the memory channel includes physical connections that are shared by at least two DIMMs.

9. The device of claim 8 , wherein the device sends the device feedback to the memory controller using the physical connections.

10. The device of claim 9 , wherein the device feedback includes access parameters for the at least two DIMMs.

11. The memory module of claim 10 , wherein the access parameters of the device feedback include a transaction ID.

12. A system comprising:

a memory controller;

a device comprising a non-volatile memory; and

a memory channel for providing an asynchronous memory interface between the memory controller and the device,

wherein the asynchronous memory interface uses the memory channel to asynchronously send a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller.

13. The system of claim 12 , wherein the memory controller synchronously sends data requested by the data access request using the memory channel based on the status of the device.

14. The system of claim 12 , wherein the memory channel includes physical connections that are dedicated to a specific dual in-line memory module (DIMM).

15. The system of claim 12 , wherein the memory channel includes physical connections that are shared by at least two DIMMs.

16. The system of claim 15 , wherein the device sends a device feedback to the memory controller using one or more physical connections.

17. The system of claim 16 , wherein the device feedback includes access parameters for the at least two DIMMs.

18. The system of claim 17 , wherein the access parameters of the device feedback include a transaction ID.

19. The system of claim 12 , wherein the device comprises a volatile memory, and the non-volatile memory and the volatile memory of the memory module are co-located in the memory channel.

20. A method comprising:

providing an asynchronous memory interface between a memory controller and a device over a memory channel that is operable for synchronous data communication between the memory controller and the memory module, wherein device comprises a non-volatile memory;

asynchronously sending a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller; and

sending the data to the memory controller via the memory channel.