IP Library › Granted Patent US 12,148,389
Granted Patent B2
US 12,148,389 · App. 17/959,260 · Granted Nov 19, 2024

Display device

Inventors: Tae Hoon Kwon (Yongin-si, KR); Ji Hyun Ka (Yongin-si, KR); Nack Hyeon Keum (Yongin-si, KR); Jae Jin Song (Yongin-si, KR); Kwang Sae Lee (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3266G09G3/22G09G2300/0413G09G2310/0264G09G2310/0286G09G2310/08G09G2330/028
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Quick Facts
Patent No.
US 12,148,389
App. No.
17/959,260
Granted
Nov 19, 2024
Kind
B2
Abstract

A gate driver including a plurality of stages, each of the plurality of stages including an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node, a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node, an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node, a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal, and a third capacitor connected between the third power input terminal and the fourth node.

Claims (60)

1. A gate driver comprising a plurality of stages, each of the plurality of stages comprising:

an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node;

a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node;

an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal;

a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; and

a third capacitor connected between the third power input terminal and the fourth node,

wherein a drain of the seventh transistor and a drain of the eighth transistors are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistors is connected to the third power input terminal.

2. The gate driver of claim 1 , each of the plurality of stages further comprising a ninth transistor, the ninth transistor including one electrode connected to the fourth node and a gate electrode connected to a third input terminal receiving a second clock signal.

3. The gate driver of claim 2 , each of the plurality of stages further comprising a tenth transistor connected between the ninth transistor and the third input terminal, the tenth transistor including a gate electrode connected to a fifth node.

4. A gate driver comprising a plurality of stages, each of the plurality of stages comprising:

an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node;

a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node;

a ninth transistor, the ninth transistor including one electrode connected to the fourth node and a gate electrode connected to a third input terminal receiving a second clock signal;

a tenth transistor connected between the ninth transistor and the third input terminal, the tenth transistor including a gate electrode connected to a fifth node;

an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal;

a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node;

a thirteenth transistor connected between a second node and the fifth node, the thirteenth transistor including a gate electrode connected to a first power input terminal; and

a third capacitor connected between the third power input terminal and the fourth node.

5. The gate driver of claim 4 , each of the plurality of stages further comprising a sixth transistor connected between the second node and the second power input terminal, the sixth transistor including a gate electrode connected to a second input terminal receiving a first clock signal.

6. The gate driver of claim 5 , each of the plurality of stages further comprising a fifth transistor connected between the second node and the second input terminal, the fifth transistor including a gate electrode connected to the first node.

7. The gate driver of claim 6 , each of the plurality of stages further comprising:

a first capacitor connected to a sixth node; and

a third transistor connected between the first capacitor and the third input terminal, the third transistor including a gate electrode connected to the sixth node.

8. The gate driver of claim 7 , each of the plurality of stages further comprising a fourth transistor connected between a first input terminal receiving a start pulse or a gate signal of a previous stage and the first node, the fourth transistor including a gate electrode connected to the second input terminal.

9. A display device comprising a pixel and a stage connected to the pixel through a gate line, wherein the stage comprises:

an eighth transistor connected between a third power input terminal and an output terminal connected to the gate line, the eighth transistor including a gate electrode connected to a fourth node;

a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node;

an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal;

a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; and

a third capacitor connected between the third power input terminal and the fourth node, and

wherein a drain of the seventh transistor and a drain of the eighth transistors are connected to the output terminal forming a node with the gate line, a drain of the seventh transistor is directly to the second power input terminal, and a source of the eighth transistor is connected to the third power input terminal.

10. The display device of claim 9 , wherein the stage further comprises a ninth transistor, the ninth transistor including one electrode connected to the fourth node and a gate electrode connected to a third input terminal receiving a second clock signal.

11. The display device of claim 10 , wherein the stage further comprises a tenth transistor connected between the ninth transistor and the third input terminal, the tenth transistor including a gate electrode connected to a fifth node.

12. A display device comprising a pixel and a stage connected to the pixel through a gate line, wherein the stage comprises:

an eighth transistor connected between a third power input terminal and an output terminal connected to the gate line, the eighth transistor including a gate electrode connected to a fourth node;

a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node;

a ninth transistor, the ninth transistor including one electrode connected to the fourth node and a gate electrode connected to a third input terminal receiving a second clock signal;

a tenth transistor connected between the ninth transistor and the third input terminal, the tenth transistor including a gate electrode connected to a fifth node;

an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal;

a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node;

a thirteenth transistor connected between a second node and the fifth node, the thirteenth transistor including a gate electrode connected to a first power input terminal; and

a third capacitor connected between the third power input terminal and the fourth node.

13. The display device of claim 12 , wherein the stage further comprises a sixth transistor connected between the second node and the second power input terminal, the sixth transistor including a gate electrode connected to a second input terminal receiving a first clock signal.

14. The display device of claim 13 , wherein the stage further comprises a fifth transistor connected between the second node and the second input terminal, the fifth transistor including a gate electrode connected to the first node.

15. The display device of claim 14 , wherein the stage further comprises:

a first capacitor connected to a sixth node; and

a third transistor connected between the first capacitor and the third input terminal, the third transistor including a gate electrode connected to the sixth node.

16. The display device of claim 15 , wherein the stage further comprises a fourth transistor connected between a first input terminal receiving a start pulse or a gate signal of a previous stage and the first node, the fourth transistor including a gate electrode connected to the second input terminal.

17. The display device of claim 9 , wherein the pixel comprises:

a fifth pixel transistor connected between a first line receiving a first driving voltage and a first pixel node, the fifth pixel transistor including a gate electrode connected to the gate line;

a first pixel transistor connected between the first pixel node and a second pixel node, the first pixel transistor including a gate electrode connected to a third pixel node;

a sixth pixel transistor connected between the second pixel node and a fourth pixel node, the sixth pixel transistor including a gate electrode connected to the gate line; and

a light emitting device connected between the fourth pixel node and a second line receiving a second driving voltage.

18. The display device of claim 17 , wherein the pixel further comprises:

a storage capacitor connected between the first line and the third pixel node; and

a second pixel transistor connected between a data line and the first pixel node, the second pixel transistor including a gate electrode connected to a first scan line.

19. The display device of claim 18 , wherein the pixel further comprises:

a third pixel transistor connected between the third pixel node and a third line receiving a first initialization voltage, the third pixel transistor including a gate electrode connected to a second scan line; and

a fourth pixel transistor connected between the second pixel node and the third pixel node, the fourth pixel transistor including a gate electrode connected to a third scan line.

20. The display device of claim 19 , wherein the pixel further comprises a seventh pixel transistor connected between the fourth pixel node and a fourth line receiving a second initialization voltage, the seventh pixel transistor including a gate electrode connected to a fourth scan line.

Priority Claims (1)
KR 10-2020-0066743 · Jun 2, 2020 · national
Continuity (2)
Continuation 17146358 · Jan 11, 2021
Related Publication 20230027500A1 · Jan 26, 2023