Memory cell in wafer backside
A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.
1. A semiconductor structure comprising:
a substrate;
a memory cell formed on a backside of the substrate;
the substrate including:
a buried metal structure connected to at least one device formed on a frontside of the substrate via an interconnect; and
a through-silicon-via (TSV) connected to the buried metal structure and the memory cell formed on the backside of the substrate, wherein the interconnect spans from a frontside metal layer on a surface of the frontside of the substrate to the buried metal structure, the buried metal structure spans from the interconnect to the TSV, and the TSV spans from the buried metal structure to a surface of the backside of the substrate.
2. The semiconductor structure of claim 1 , wherein the memory cell is an analog memory cell.
3. The semiconductor structure of claim 1 , wherein the memory cell is a phase change memory (PCM) cell.
4. The semiconductor structure of claim 1 , wherein the buried metal structure is composed of one of Cobalt (Co), Tungsten (W), Ruthenium (Ru).
5. The semiconductor structure of claim 1 , wherein the TSV is a nano-TSV.
6. The semiconductor structure of claim 1 , wherein the at least one device includes at least one transistor.
7. The semiconductor of claim 1 , wherein:
the memory cell is connected to a backside metal layer that connects to a read line of a memory device; and
the frontside metal layer is form on a frontside of the substrate, the frontside metal layer being connected to a bit line of the memory device.