Work function design to increase density of nanosheet devices

1. An integrated chip, comprising:

a first channel structure within a first transistor device;

a first gate electrode layer wrapping around the first channel structure;

a second channel structure within a second transistor device;

a second gate electrode layer wrapping around the second channel structure, wherein the second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer;

a third channel structure within a third transistor device; and

a third gate electrode layer wrapping around the third channel structure, wherein the third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

2. The integrated chip of claim 1 , wherein the first transistor device comprises an n-type field effect transistor, the second transistor device comprises a p-type field effect transistor, and the third transistor device comprises a p-type field effect transistor.

3. The integrated chip of claim 1 , wherein the first channel structure extends between a first source/drain region and a second source/drain region.

4. The integrated chip of claim 1 , further comprising:

a first gate dielectric layer continuously wrapping around the first channel structure and separating the first channel structure from the first gate electrode layer, wherein the first gate dielectric layer comprises lanthanum, magnesium, yttrium, aluminum, niobium, or titanium.

5. The integrated chip of claim 1 , further comprising:

a substrate including sidewalls that form a first fin, a second fin, and a third fin, wherein the first channel structure is directly over the first fin, the second channel structure is directly over the second fin, and the third channel structure is directly over the third fin.

6. The integrated chip of claim 5 , further comprising:

a first gate dielectric layer and a first interfacial layer vertically between the first fin and the first channel structure, wherein the first interfacial layer continuously extends between a lower surface of the first gate dielectric layer and an upper surface of the first fin.

7. An integrated chip, comprising:

a first channel structure configured to extend between a first source/drain region and a second source/drain region;

a first gate electrode layer wrapping around the first channel structure in a first closed loop;

a second channel structure configured to extend between a third source/drain region and a fourth source/drain region;

a second gate electrode layer wrapping around the second channel structure in a second closed loop, wherein the second gate electrode layer continuously extends from around the second channel structure to on the first gate electrode layer; and

wherein the second channel structure is part of a nanosheet SRAM device within an SRAM cell.

8. The integrated chip of claim 7 , wherein the first channel structure is part of an n-type field effect transistor and the second channel structure is part of a p-type field effect transistor.

9. The integrated chip of claim 7 , further comprising:

an upper channel structure directly over the first channel structure, the upper channel structure being separated from the first channel structure by a distance of approximately 12 nanometers (nm).

10. The integrated chip of claim 7 , further comprising:

a third gate electrode layer covering the first gate electrode layer and the second gate electrode layer, the second gate electrode layer being laterally and vertically between the first gate electrode layer and the third gate electrode layer.

11. The integrated chip of claim 7 , further comprising:

a third channel structure configured to extend between a fifth source/drain region and a sixth source/drain region; and

a third gate electrode layer wrapping around the third channel structure in a third closed loop, wherein the third gate electrode layer continuously extends from around the third channel structure to on the second gate electrode layer.

12. A method of forming an integrated chip comprising:

forming a first plurality of channel structures over a substrate;

forming a second plurality of channel structures over the substrate;

forming a mask vertically between the first plurality of channel structures and vertically between the second plurality of channel structures;

removing the mask from between the first plurality of channel structures;

forming a first gate electrode layer on the first plurality of channel structures, on the second plurality of channel structures, and on sidewalls of the mask between the second plurality of channel structures;

removing the first gate electrode layer from over the second plurality of channel structures and subsequently removing the mask from between the second plurality of channel structures; and

forming a second gate electrode layer on the first gate electrode layer and the second plurality of channel structures after removing the mask from between the second plurality of channel structures.

13. The method of claim 12 , wherein the first plurality of channel structures are configured to transport charge carriers within a first transistor device and the second plurality of channel structures are configured to transport charge carriers within a second transistor device.

14. The method of claim 12 , further comprising:

forming an additional masking structure over the second plurality of channel structures; and

removing the mask from vertically between the first plurality of channel structures with the additional masking structure over the second plurality of channel structures.

15. The method of claim 12 , wherein the mask is completely confined below one or more of the first plurality of channel structures.

16. The method of claim 12 , further comprising:

forming a gate dielectric onto the first plurality of channel structures prior to forming the mask.

17. The method of claim 16 , wherein the gate dielectric laterally extends past an outermost edge of the mask.

18. The method of claim 12 , wherein the mask comprises aluminum oxide or titanium nitride.

19. The method of claim 12 , wherein the second gate electrode layer is formed on the first gate electrode layer and the second plurality of channel structures after removing the mask from between the second plurality of channel structures.

20. The method of claim 12 , further comprising:

forming the mask over and along sidewalls of both the first plurality of channel structures and the second plurality of channel structures; and

removing the mask from the sidewalls of the first plurality of channel structures and the second plurality of channel structures prior to removing the mask from between the first plurality of channel structures.