Semiconductor devices
In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.
1. A device comprising:
a first dielectric layer;
a channel region over the first dielectric layer;
a gate structure over the channel region;
a source/drain region adjacent the gate structure;
a second dielectric layer over the source/drain region; and
a conductive via extending through the second dielectric layer and the first dielectric layer, a top surface of the conductive via being coplanar with a top surface of the gate structure.
2. The device of claim 1 , further comprising:
a first interconnect structure below the first dielectric layer, the first interconnect structure comprising a power rail; and
a second interconnect structure above the second dielectric layer, the second interconnect structure comprising a conductive line, the conductive via connecting the power rail to the conductive line.
3. The device of claim 1 , wherein a bottom surface of the conductive via is coplanar with a bottom surface of the first dielectric layer, and the top surface of the conductive via is coplanar with a top surface of the second dielectric layer.
4. The device of claim 1 , wherein the conductive via extends through the source/drain region.
5. The device of claim 4 , further comprising:
a metal-semiconductor alloy region around a portion of the conductive via extending through the source/drain region.
6. The device of claim 1 , wherein the conductive via comprises:
a first source/drain contact extending through the first dielectric layer and into a lower portion of the source/drain region; and
a second source/drain contact extending through the second dielectric layer and into an upper portion of the source/drain region, the second source/drain contact physically and electrically coupled to the first source/drain contact.
7. The device of claim 1 , wherein the conductive via extends along a sidewall of the source/drain region.
8. The device of claim 7 , further comprising:
a metal-semiconductor alloy region disposed between the conductive via and the sidewall of the source/drain region.
9. The device of claim 1 , wherein the conductive via comprises:
a first source/drain contact extending through the first dielectric layer; and
a second source/drain contact extending through the second dielectric layer, the second source/drain contact extending along a sidewall of the source/drain region.
10. A device comprising:
a first interconnect structure comprising a conductive line;
a second interconnect structure comprising a power rail;
a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising a transistor; and
a conductive via extending through the device layer, the conductive via connecting the power rail to the conductive line.
11. The device of claim 10 , wherein the transistor comprises a source/drain region, and the conductive via extends through the source/drain region.
12. The device of claim 10 , wherein the transistor comprises a source/drain region, and the conductive via extends along and contacts a bottom surface and a sidewall of the source/drain region.
13. The device of claim 10 , wherein the transistor comprises a source/drain region, and the conductive via extends along and contacts a bottom surface of the source/drain region, and extends along and is physically separated from a sidewall of the source/drain region.
14. The device of claim 10 , wherein a width of the power rail is greater than a width of the conductive line.
15. A device comprising:
a first interconnect structure comprising metallization patterns;
a second interconnect structure comprising power rails;
a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising active devices, the metallization patterns interconnecting the active devices to form functional circuits, the power rails providing a reference/supply voltage to the functional circuits; and
a conductive via extending through the device layer, the conductive via connecting one of the power rails to one of the metallization patterns.
16. The device of claim 15 , wherein the active devices comprise source/drain regions, and the device layer further comprises:
a first dielectric layer; and
a second dielectric layer, the source/drain regions located between the second dielectric layer and the first dielectric layer, the conductive via extending through the second dielectric layer and the first dielectric layer.
17. The device of claim 16 , wherein the conductive via is physically and electrically coupled to one of the source/drain regions.
18. The device of claim 16 , wherein the conductive via extends through one of the source/drain regions.
19. The device of claim 16 , wherein the conductive via extends along a sidewall of one of the source/drain regions.
20. The device of claim 15 , wherein a width of the one of the power rails is greater than a width of the one of the metallization patterns.