Dynamic error quantizer tuning systems and methods
Dynamic error-quantizer tuning systems and methods prevent misconvergence to local minima by using a dynamic quantizer circuit that controls reference voltages of three or more comparators that are independently adjusted to modify the transfer function of the dynamic quantizer circuit. A weighted sum of the comparator outputs is subtracted from the input to form an error signal in a control loop. The ratio of the reference voltages is chosen to reduce or eliminate local minima during a convergence of the control loop and is set to values that minimize a mean squared error signal with respect to discrete modulation states of the input after the convergence of the control loop is complete.
1. A polarization and carrier phase correction circuit comprising:
error quantizers that use an error signal and an ideal modulation constellation to generate comparison results;
complex adaption circuits that use the comparison results in a control loop to adjust a set of tap weights;
analog complex multipliers that apply the tap weights to a set of input signals to correct for polarization and phase changes in at least one optical channel; and
a control circuit that, in response to detecting that an amplitude on at least one signal in the set of input signals representing matrix coefficients is at or below a threshold, causes the error quantizers to operate in a first mode of operation and, in response to determining that the control loop satisfies a convergence criterion, causes the error quantizers to operate in a second mode of operation to reduce a time-varying signal error that causes a tap weight noise.
2. The circuit according to claim 1 , wherein the tap weights represent coefficients of a complex 2×2 matrix.
3. The circuit according to claim 1 , further comprising switches coupled to the error quantizers and the complex adaption circuits and, in response to a least-mean-square (LMS) enable signal, switching between the first and second modes of operation.
4. The circuit according to claim 1 , wherein the first mode of operation is one of a convergence mode or a non-return-to-zero (NRZ) mode and wherein the second mode of operation comprises one of a tracking mode or a regular mode.
5. The circuit according to claim 4 , wherein the first mode of operation causes data slicing to generate binary symbol decisions.
6. The circuit according to claim 1 , wherein the control circuit is implemented by a unitary forcer circuit.
7. The circuit according to claim 1 , wherein the error quantizers comprise comparator circuits that generates the comparison results.
8. The circuit according to claim 1 , wherein the complex adaption circuits use an LMS update equation when adjusting the set of tap weights.
9. The circuit according to claim 1 , further comprising, a ramp generator that generates a ramp from an initial voltage to a target voltage, the ramp being asymmetric around a zero value.