IP Library Granted Patent US 12,153,530
Granted Patent B2
US 12,153,530 · App. 18/298,386 · Granted Nov 26, 2024

Data processing system allocating memory area in host as extension of memory and operating method thereof

Inventor: Jong-Min Lee (Seoul, KR)
Assignee: SK hynix Inc.
G06F13/1668G06F3/0604G06F3/0659G06F3/0673G06F13/4282G06F2213/0016
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Quick Facts
Patent No.
US 12,153,530
App. No.
18/298,386
Granted
Nov 26, 2024
Kind
B2
Abstract

A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Claims (34)

1. A memory system, comprising:

a plurality of nonvolatile memory dies; and

a controller configured to control the plurality of nonvolatile memory dies to perform a data program operation or a data read operation,

wherein the controller monitors a usage status of a volatile memory in the memory system, and transmits, to a host, a request or a response for using a memory resource which exists outside the memory system as an extension of the volatile memory in the memory system based on a result of the monitoring,

wherein the controller uses the memory resource to store operation information required for the data program operation or the data read operation, and

wherein the operation information includes a die structure of the plurality of nonvolatile memory dies and the number of the nonvolatile memory dies in the memory system.

2. The memory system according to claim 1 , wherein the volatile memory exists in the controller.

3. The memory system according to claim 1 , wherein the volatile memory exists outside the controller.

4. A memory system, comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device to perform a data program operation or a data read operation, requested by a host, and control a volatile memory in the memory system,

wherein the controller accesses a memory resource which is engaged with the host, exists outside the memory system, and is allocated to the controller as an extension of the volatile memory by a host, and

wherein the controller uses the memory resource to store a logical/physical mapping information for the data program operation or the data read operation.

5. The memory system according to claim 4 , wherein the memory resource is allocated to the controller by the host based on a request or a response transmitted from the controller.

6. The memory system according to claim 4 , wherein the volatile memory exists in the controller.

7. The memory system according to claim 4 , wherein the volatile memory exists outside the controller.

8. The memory system according to claim 7 , wherein the controller further uses the memory resource to store erase counts for a plurality of memory blocks in the nonvolatile memory device.

9. A memory system, comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device to perform a data program operation or a data read operation, control a volatile memory in the memory system for the data program operation or the data read operation, and monitor a status of the volatile memory,

wherein the controller accesses a host memory resource which exists outside the memory system, and is engaged with a host and allocated to the controller by the host based on the monitoring, and

wherein the controller stores, in the host memory resource, logical/physical mapping information for the data program operation or the data read operation.

10. The memory system according to claim 9 , wherein the memory resource is allocated to the controller by the host based on a request or a response transmitted from the controller.

11. The memory system according to claim 9 , wherein the volatile memory exists in the controller.

12. The memory system according to claim 9 , wherein the volatile memory exists outside the controller.

13. The memory system according to claim 12 , wherein the controller further uses the extended volatile memory to store erase counts of a plurality of memory blocks in the nonvolatile memory device.

14. A memory system, comprising:

a plurality of non-volatile memory dies; and

a controller, including or coupled to a volatile memory, configured to control a data input/output operation which is requested by a host and performed in the non-volatile memory dies,

wherein the controller accesses or uses a memory resource, as an extension of the volatile memory, for storing operation information associated with the plurality of non-volatile memory dies and the data input/output operation, and

wherein the memory resource is engaged by the host outside the memory system and allocated to the controller based on a request or response transmitted from the controller.

15. The memory system according to claim 14 , wherein the operation information comprises a die structure of the plurality of non-volatile memory dies and the number of the nonvolatile memory dies in the memory system.

16. The memory system according to claim 14 , wherein the operation information comprises erase counts of a plurality of memory blocks included in the plurality of non-volatile memory dies.

17. The memory system according to claim 14 , wherein the operation information comprises logical/physical mapping information for the input/output operation and the plurality of non-volatile memory dies.

Priority Claims (1)
KR 10-2018-0091319 · Aug 6, 2018 · national
Continuity (4)
Continuation 17713001 · Apr 4, 2022
Continuation 17122461 · Dec 15, 2020
Division 16367974 · Mar 28, 2019
Related Publication 20230244616A1 · Aug 3, 2023