Processor with macro-instruction achieving zero-latency data movement
An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.
1. An apparatus comprising:
a hardware array processor to process array data in response to a macro-instruction,
wherein the hardware array processor processes the array data using loop operations, array iteration operations, and arithmetic logic unit (ALU) operations defined by the macro-instruction to achieve zero-latency data movement.
2. The apparatus according to claim 1 , wherein the loop operations, the array iteration operations, and the ALU operations form an atomic action sequence.
3. The apparatus according to claim 2 , wherein the atomic action sequence uses variables corresponding to array element values accessed using predetermined memory access patterns.
4. The apparatus according to claim 1 , wherein the macro-instruction causes the hardware array processor to perform the loop operations, wherein the loop operations include begin loop, end loop, and exit loop operations.
5. The apparatus according to claim 1 , wherein the array iteration operations include loading a set of registers from a defined array.
6. The apparatus according to claim 5 , where the defined array is defined with per-dimension size and stride values.
7. The apparatus according to claim 1 , wherein the macro-instruction is a compound instruction comprising input-output controls, loop controls, ALU controls, and a base instruction operational code.
8. The apparatus according to claim 1 , wherein the macro-instruction is executed in one clock cycle of the hardware array processor.
9. The apparatus according to claim 1 ,
wherein the macro-instruction is included in a set of macro-instructions executable by the hardware array processor, and
wherein the set of macro-instructions has no conditional instructions.
10. The apparatus according to claim 1 , further comprising:
a memory coupled to the hardware array processor for access by the hardware array processor, and
wherein a memory access pattern for a given program for the hardware array processor is pre-determined.
11. The apparatus according to claim 1 ,
wherein the macro-instruction is one of a set of macro-instructions, and
wherein each macro-instruction of the set of macro-instructions includes an input-output control field, a loop control field, an ALU control field, and an opcode.
12. An apparatus, comprising:
an array processor, comprising:
a control circuit; and
a data pipeline,
wherein the control circuit decodes a macro-instruction to cause the array processor to use loop operations, array iteration operations, and arithmetic logic unit (ALU) operations to perform a computation per array element of an array stored in a memory, the computation per array element being performed with zero-latency data movement.
13. The apparatus according to claim 12 , wherein the control circuit includes an array controller.
14. The apparatus according to claim 12 , wherein the control circuit includes an instruction sequencer to control a flow of and execute instructions associated with the macro-instruction.
15. The apparatus according to claim 12 further comprising:
the memory,
wherein the memory is coupled to the array processor for access by the array processor, and
wherein a memory access pattern for a given program for the array processor is pre-determined.
16. The apparatus according to claim 15 , wherein the array processor is pipelined to a level to accommodate performing the loop operations and the array iteration operations with zero-latency data movement.
17. A method of processing array data, the method comprising:
using an array processor to process the array data in response to a macro-instruction,
wherein the array data is stored in a memory and the array processor performs an operation on the array data using loop operations, array iteration operations, and arithmetic logic unit (ALU) operations defined by the macro-instruction to achieve zero-latency data movement.
18. The method according to claim 17 , wherein the loop operations, the array iteration operations, and the ALU operations form an atomic action sequence.
19. The method according to claim 17 , wherein the loop operations include begin loop, end loop, and exit loop operations.
20. The method according to claim 17 , wherein the array iteration operations include loading a set of registers from a defined array, and wherein the defined array is defined with per-dimension size and stride values.
21. The method according to claim 17 , wherein the macro-instruction is executed in one clock cycle of the array processor.
22. The method according to claim 17 , wherein the macro-instruction is one of a set of macro-instructions including no conditional instructions.