Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems
Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
1. A microelectronic device, comprising:
a package substrate;
a die coupled to a top side of the package substrate;
a main patch in the top surface of the package substrate; and
a mold material having a first portion laterally adjacent to the die and a second portion over the main patch, the first portion of the mold material having a first thickness, and the second portion of the mold material having a second thickness, the second thickness greater than the first thickness.
2. The microelectronic device of claim 1 , wherein the first portion of the mold material is further over the die.
3. The microelectronic device of claim 1 , wherein the die has an uppermost surface above the first portion of the mold material.
4. The microelectronic device of claim 3 , further comprising:
a heat sink coupled to the uppermost surface of the die.
5. The microelectronic device of claim 4 , wherein the heat sink has an uppermost surface below an uppermost surface of the second portion of the mold material.
6. The microelectronic device of claim 1 , further comprising:
a parasitic patch on the second portion of the mold material.
7. The microelectronic device of claim 6 , wherein the parasitic patch is vertically over the main patch.
8. The microelectronic device of claim 6 , wherein the parasitic patch is capacitively coupled with the main patch.
9. The microelectronic device of claim 1 , wherein the die is an RF die.
10. The microelectronic device of claim 1 , wherein the package substrate comprises a ground plane.
11. The microelectronic device of claim 10 , wherein the ground plane extends vertically beneath the die and vertically beneath the main patch.
12. The microelectronic device of claim 1 , further comprising:
a plurality of solder balls on a bottom side of the package substrate, the bottom side opposite the top side.
13. A microelectronic device, comprising:
a substrate having radio frequency (RF) components;
a package substrate having a bottom side coupled to the substrate by a plurality of solder balls;
a die coupled to a top side of the package substrate, the top side opposite the bottom side;
a main patch in the top surface of the package substrate; and
a mold material having a first portion laterally adjacent to the die and a second portion over the main patch, the first portion of the mold material having a first thickness, and the second portion of the mold material having a second thickness, the second thickness greater than the first thickness.
14. The microelectronic device of claim 13 , wherein the substrate comprises one or more integrated passive devices (IPDs).
15. The microelectronic device of claim 13 , wherein the substrate is a board.
16. The microelectronic device of claim 13 , wherein the first portion of the mold material is further over the die.
17. The microelectronic device of claim 13 , wherein the die has an uppermost surface above the first portion of the mold material.
18. The microelectronic device of claim 17 , further comprising:
a heat sink coupled to the uppermost surface of the die, wherein the heat sink has an uppermost surface below an uppermost surface of the second portion of the mold material.
19. The microelectronic device of claim 13 , further comprising:
a parasitic patch on the second portion of the mold material.
20. The microelectronic device of claim 19 , wherein the parasitic patch is vertically over the main patch.