Characterizing and margining multi-voltage signal encoding for interconnects
Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.
1. An apparatus comprising:
a receiver comprising:
margin control and status registers;
a port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes;
error detection circuitry to detect an error in the Flit, the error detection circuitry comprising forward error correction (FEC) circuitry,
an error counter to count a number of errors detected, the error counter to increment based on the error detected in the Flit by the error detection circuitry,
a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving the Flit, and
bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter;
wherein bits of the margin control and status registers indicate whether a test mode is activated, and the receiver is to log the bit error rate based on the test mode being indicated as activated.
2. The apparatus of claim 1 , wherein the FEC circuitry to correct the error in the Flit with error correcting code.
3. The apparatus of claim 2 , wherein the error counter is to increment based on the FEC circuitry correcting the error in the Flit.
4. The apparatus of claim 2 , wherein the error detection circuitry further comprises cyclic redundancy check (CRC) circuitry, and the error counter to increment based on the FEC circuitry correcting the error in the Flit and the Flit passing a check performed by the CRC circuitry.
5. The apparatus of claim 2 , wherein the FEC circuitry is to detect a correctable error in the Flit on a per-lane basis, and wherein the error counter is to count a number of correctable errors on a per-lane basis.
6. The apparatus of claim 1 , wherein the error detection circuitry further comprises cyclic redundancy check (CRC) circuitry, the CRC circuitry to detect an uncorrectable error in the Flit, and wherein the error counter comprises an uncorrectable error counter, the uncorrectable error counter to increment based on the Flit comprising an uncorrectable error.
7. The apparatus of claim 1 , wherein the error detection circuitry comprises ordered set (OS) parity check circuitry to detect an error in an OS based on a parity mismatch, and wherein the error counter is to count the error detected by the OS parity check circuitry.
8. The apparatus of claim 1 , wherein the error counter is to count a first error detected at after a Flit boundary.
9. The apparatus of claim 1 , wherein the error counter is to count each error in the Flit.
10. The apparatus of claim 1 , further comprising a margin command register, the margin command register comprising margin command information to start, stop, or clear the error counter.
11. A method comprising:
activating a test mode by setting bits in margin control and status registers of a Peripheral Component Interconnect Express (PCIe)-compatible device;
receiving, at the PCIe-compatible device, a Flit from a multilane link;
detecting an error in the Flit by error detection circuitry comprising forward error correction (FEC) circuitry;
incrementing an error counter based on determining the error and based on a type of error;
incrementing a Flit counter;
determining a bit error rate based on an error count recorded by the error counter and a number of bits received recorded by the Flit counter; and
logging the bit error rate.
12. The method of claim 11 , wherein determining an error in the Flit comprises:
detecting a correctable error by the forward error correction (FEC) circuitry; and
correcting the correctable error using error correcting code.
13. The method of claim 12 , wherein incrementing the error counter comprises incrementing a per-lane correctable error counter based on correcting the correctable error using error correcting code.
14. The method of claim 12 , wherein incrementing the error counter comprises incrementing a per-lane correctable error counter based on correcting the correctable error using error correcting code and the Flit passing a cyclic redundancy check.
15. The method of claim 12 , further comprising incrementing a per-lane correctable error counter for errors corrected on each lane of the multilane link.
16. The method of claim 11 , further comprising:
determining an uncorrectable error in the Flit; and
incrementing the error counter comprises incrementing a per-port uncorrectable error counter based on determining the uncorrectable error in the Flit.
17. The method of claim 11 , further comprising:
determining an error in an ordered set at an ordered set boundary based on a parity mismatch;
incrementing the error counter based on determining the error in the ordered set.
18. The method of claim 11 , wherein incrementing the error counter comprises incrementing the error counter based on each error detected in the Flit.
19. The method of claim 11 , wherein incrementing the error counter comprises incrementing the error counter based on a first error detected in the Flit.
20. The method of claim 11 , further comprising setting information in a margin command register to start, stop, or clear the error counter.
21. A system comprising:
a host device comprising a transmitter to transmit a flow control unit (Flit) over a multilane link;
an endpoint device comprising a receiver port to receive the Flit, the receiver port comprising:
margin control and status registers;
forward error correction (FEC) circuitry to detect an error in the Flit,
an error counter to count a number of errors detected, the error counter to increment based on the error detected in the Flit by the FEC circuitry,
a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving the Flit, and
bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter, wherein the receiver port is to log the bit error rate based on one or more bits of the margin control and status registers indicating a test mode is activated.
22. The system of claim 21 , further comprising a retimer coupled by a multilane link downstream of the host device and upstream of the endpoint device, the retimer comprising:
ordered set (OS) error detection circuitry to detect an OS error at a Flit boundary; and
an OS error counter to count a number of OS errors detected, the OS error counter to increment based on an OS error detected at a Flit boundary based on a parity mismatch.
23. The system of claim 22 , further comprising a margin command register comprising information to start, stop, or clear the error counter or the OS error counter.
24. The system of claim 21 , wherein the FEC circuitry to correct the error in the Flit with error correcting code; and wherein the error counter is to increment based on the FEC circuitry correcting the error in the Flit.
25. The system of claim 24 , the receiver port further comprising cyclic redundancy check (CRC) circuitry, the error counter to increment based on the FEC circuitry correcting the error in the Flit and the Flit passing a check performed by the CRC circuitry.