Circuitry and methods for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array

1. An apparatus comprising:

a two-dimensional grid of compute circuits;

a memory;

a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits;

a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field; and

an execution circuit to execute the decoded single instruction according to the fields.

2. The apparatus of claim 1 , wherein the single instruction further comprises a field to indicate a delay time to wait before pushing first values of the two-dimensional data to each corresponding input port of the two-dimensional grid of compute circuits.

3. The apparatus of claim 2 , wherein the single instruction further comprises a field to indicate a data value that is to be pushed into each corresponding input port of the two-dimensional grid of compute circuits during the delay time.

4. The apparatus of claim 1 , wherein the single instruction further comprises a field that when set to a first value causes the two-dimensional data to be sent to a first proper subset of input ports of the two-dimensional grid of compute circuits, and when set to a second different value causes the two-dimensional data to be sent to a second different proper subset of input ports of the two-dimensional grid of compute circuits.

5. The apparatus of claim 1 , wherein the single instruction further comprises a field that when set to a multicast value causes a single element of the two-dimensional data to be sent to a plurality of compute circuits of the two-dimensional grid of compute circuits.

6. The apparatus of claim 1 , wherein a value from the fourth field that identifies the operation is passed from a first compute circuit to a second compute circuit of the two-dimensional grid of compute circuits.

7. The apparatus of claim 1 , wherein the single instruction further comprises a field that when set to a first value indicates the direct memory access circuit is to perform address generation for each element of the two-dimensional data as row major, and when set to a second different value indicates the direct memory access circuit is to perform the address generation for each element of the two-dimensional data as column major.

8. The apparatus of claim 1 , wherein:

the decoder circuit is to decode a second single instruction into a decoded second single instruction, the second single instruction including a first field to identify a base address for two-dimensional data to be stored in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data to be stored in the memory, a third field to identify a number of one-dimensional arrays of the two-dimensional data to be stored in the memory, a fourth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field from the two-dimensional grid of compute circuits into the memory; and

the execution circuit to execute the decoded second single instruction according to the fields.

9. A method comprising:

decoding a single instruction with a decoder circuit, of a processor comprising a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits, into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field; and

executing the decoded single instruction with an execution circuit of the processor according to the fields.

10. The method of claim 9 , wherein the single instruction further comprises a field to indicate a delay time to wait before pushing first values of the two-dimensional data to each corresponding input port of the two-dimensional grid of compute circuits.

11. The method of claim 10 , wherein the single instruction further comprises a field to indicate a data value that is to be pushed into each corresponding input port of the two-dimensional grid of compute circuits during the delay time.

12. The method of claim 9 , wherein the single instruction further comprises a field that when set to a first value causes the two-dimensional data to be sent to a first proper subset of input ports of the two-dimensional grid of compute circuits, and when set to a second different value causes the two-dimensional data to be sent to a second different proper subset of input ports of the two-dimensional grid of compute circuits.

13. The method of claim 9 , wherein the single instruction further comprises a field that when set to a multicast value causes a single element of the two-dimensional data to be sent to a plurality of compute circuits of the two-dimensional grid of compute circuits.

14. The method of claim 9 , wherein a value from the fourth field that identifies the operation is passed from a first compute circuit to a second compute circuit of the two-dimensional grid of compute circuits.

15. The method of claim 9 , wherein the single instruction further comprises a field that when set to a first value indicates the direct memory access circuit is to perform address generation for each element of the two-dimensional data as row major, and when set to a second different value indicates the direct memory access circuit is to perform the address generation for each element of the two-dimensional data as column major.

16. The method of claim 9 , further comprising:

decoding a second single instruction with the decoder circuit into a decoded second single instruction, the second single instruction including a first field to identify a base address for two-dimensional data to be stored in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data to be stored in the memory, a third field to identify a number of one-dimensional arrays of the two-dimensional data to be stored in the memory, a fourth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field from the two-dimensional grid of compute circuits into the memory; and

executing the decoded second single instruction with the execution circuit according to the fields.

17. An apparatus comprising:

a first type of hardware processor core comprising:

a two-dimensional grid of compute circuits,

a memory, and

a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and

a second different type of hardware processor core coupled to the first type of hardware processor core and comprising:

a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and

an execution circuit to execute the decoded single instruction according to the fields.

18. The apparatus of claim 17 , wherein the single instruction further comprises a field to indicate a delay time to wait before pushing first values of the two-dimensional data to each corresponding input port of the two-dimensional grid of compute circuits.

19. The apparatus of claim 18 , wherein the single instruction further comprises a field to indicate a data value that is to be pushed into each corresponding input port of the two-dimensional grid of compute circuits during the delay time.

20. The apparatus of claim 17 , wherein the single instruction further comprises a field that when set to a first value causes the two-dimensional data to be sent to a first proper subset of input ports of the two-dimensional grid of compute circuits, and when set to a second different value causes the two-dimensional data to be sent to a second different proper subset of input ports of the two-dimensional grid of compute circuits.

21. The apparatus of claim 17 , wherein the single instruction further comprises a field that when set to a multicast value causes a single element of the two-dimensional data to be sent to a plurality of compute circuits of the two-dimensional grid of compute circuits.

22. The apparatus of claim 17 , wherein a value from the fourth field that identifies the operation is passed from a first compute circuit to a second compute circuit of the two-dimensional grid of compute circuits.

23. The apparatus of claim 17 , wherein the single instruction further comprises a field that when set to a first value indicates the direct memory access circuit is to perform address generation for each element of the two-dimensional data as row major, and when set to a second different value indicates the direct memory access circuit is to perform the address generation for each element of the two-dimensional data as column major.

24. The apparatus of claim 17 , wherein:

the decoder circuit is to decode a second single instruction into a decoded second single instruction, the second single instruction including a first field to identify a base address for two-dimensional data to be stored in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data to be stored in the memory, a third field to identify a number of one-dimensional arrays of the two-dimensional data to be stored in the memory, a fourth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field from the two-dimensional grid of compute circuits into the memory; and

the execution circuit to execute the decoded second single instruction according to the fields.