Method of manufacturing a semiconductor package having conductive pillars
View Patent ↗A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.
1. A method comprising:
forming a redistribution structure on a carrier;
plating a plurality of conductive pillars extending from a first side of the redistribution structure;
forming first solder bumps on the plurality of conductive pillars, wherein the first solder bumps have a width that is less than a width of the conductive pillars;
connecting a routing substrate to the plurality of conductive pillars using the first solder bumps;
depositing a molding material between the redistribution structure and the routing substrate;
removing the carrier; and
after removing the carrier, connecting a semiconductor device to a second side of the redistribution structure.
2. The method of claim 1 , wherein forming the first solder bumps on the plurality of conductive pillars comprises depositing solder material on the plurality of conductive pillars and performing a reflow process on the solder material.
3. The method of claim 1 , wherein forming the first solder bumps on the plurality of conductive pillars comprises placing solder balls on the conductive pillars of the plurality of conductive pillars.
4. The method of claim 1 , further comprising connecting an integrated passive device (IPD) to the first side of the redistribution structure.
5. The method of claim 1 , wherein connecting the routing substrate to the plurality of conductive pillars using the first solder bumps comprises bonding the first solder bumps to corresponding second solder bumps on the routing substrate.
6. The method of claim 1 , wherein the molding material covers sidewalls of the routing substrate.
7. The method of claim 1 , wherein a height of the first solder bumps is less than a height of the conductive pillars.
8. A method comprising:
forming a plurality of first copper pillars on a first metallization layer on a first side of a first interconnect structure, wherein the plurality of first copper pillars protrude from the first side of the first interconnect structure, wherein a height of the first copper pillars is greater than a height of the first metallization layer;
forming a plurality of first solder caps on the plurality of first copper pillars;
performing a first reflow process on the plurality of first solder caps;
forming a plurality of second copper pillars on a second metallization layer on a first side of a second interconnect structure, wherein the plurality of second copper pillars protrude from the first side of the second interconnect structure, wherein a height of the second copper pillars is greater than a height of the second metallization layer;
forming a plurality of second solder caps on the plurality of second copper pillars;
after performing the first reflow process on the plurality of first solder caps, bonding the plurality of first solder caps to the plurality of second solder caps, comprising performing a second reflow process; and
surrounding the plurality of first copper pillars and the plurality of second copper pillars with an underfill material.
9. The method of claim 8 , wherein forming the plurality of first solder caps comprises plating a solder material on the plurality of first copper pillars.
10. The method of claim 8 , wherein the first interconnect structure comprises a core substrate.
11. The method of claim 8 further comprising forming a plurality of third copper pillars on a second side of the second interconnect structure, wherein the plurality of third copper pillars protrude from the second side of the second interconnect structure.
12. The method of claim 11 further comprising bonding a semiconductor die to the plurality of third copper pillars.
13. The method of claim 11 , wherein the third copper pillars have a width that is smaller than a width of the second copper pillars.
14. The method of claim 8 , wherein each first copper pillar has a height that is less than its width.
15. The method of claim 8 , wherein after performing the first reflow process, each first solder cap has a width that is less than a width of its underlying first copper pillar.
16. A method comprising:
depositing a first dielectric layer over a redistribution layer of a redistribution structure;
patterning the first dielectric layer to expose portions of the redistribution layer;
forming a plurality of conductive posts on the first dielectric layer and the exposed portions of redistribution layer, comprising:
depositing a seed layer over the first dielectric layer and the exposed portions of the redistribution layer;
depositing a photoresist over the seed layer;
patterning a plurality of openings in the photoresist that expose the seed layer; and
plating a metal into the plurality of openings;
plating a solder material into the plurality of openings; and
bonding an interconnect structure to the solder material.
17. The method of claim 16 further comprising bonding a semiconductor device to the redistribution structure opposite the interconnect structure.
18. The method of claim 16 further comprising performing a reflow process on the solder material before bonding the interconnect structure to the solder material.
19. The method of claim 16 further comprising connecting an integrated passive device (IPD) to the redistribution layer before bonding the interconnect structure to the solder material.
20. The method of claim 16 further comprising depositing a molding material between the interconnect structure and the redistribution structure.