Switching time reduction of an RF switch

1. A switch assembly for a radio frequency signal, the switch assembly comprising:

a first node coupled to an input of the switch assembly, a second node coupled to an output of the switch assembly, a first control node, and a common node;

a first switch having a first plurality of transistors coupled between the first and second nodes, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to the common node;

a common resistor coupled between the first control node and the common node;

a second switch coupled between the first control node and the common node in parallel to the common resistor, the second switch configured to selectively bypass the common resistor;

a voltage level shifter coupled between the first control node and the second switch, the voltage level shifter configured to output a positive voltage and a negative voltage; and

a control resistor coupled between the first control node and the second switch.

2. A switch assembly for a radio frequency signal, the switch assembly comprising:

a first node coupled to an input of the switch assembly, a second node coupled to an output of the switch assembly, a first control node, and a common node;

a first switch having a first plurality of transistors coupled between the first and second nodes, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to the common node;

a common resistor coupled between the first control node and the common node;

a second switch coupled between the first control node and the common node in parallel to the common resistor, the second switch configured to selectively bypass the common resistor; and

a voltage level shifter coupled between the first control node and the second switch, the voltage level shifter configured to output a positive voltage and a negative voltage.

3. The switch assembly of claim 2 wherein a first control signal received by the first control node is applied to the gates of the first plurality of transistors through the second switch and/or through the common resistor.

4. The switch assembly of claim 3 wherein the first control signal is configured to operate the first switch in an ON state by turning on each of the first plurality of transistors such that a radio frequency signal received at the first node is provided to the second node.

5. The switch assembly of claim 3 wherein the first control signal is configured to operate the first switch in an OFF state by turning off each of the first plurality of transistors such that a radio frequency signal received at the first node is not provided to the second node.

6. The switch assembly of claim 3 further comprising a second control node coupled to the second switch.

7. The switch assembly of claim 6 wherein a second control signal received by the second control node is configured to operate the second switch in an OFF state such that the first control signal is applied to the gates of the first plurality of transistors through the common resistor.

8. The switch assembly of claim 6 wherein a second control signal received by the second control node is configured to operate the second switch in an ON state such that the common resistor is shorted and such that the first control signal is applied to the gates of the first plurality of transistors through the second switch.

9. The switch assembly of claim 8 wherein the second control signal is configured to operate the second switch in the ON state whilst the first control signal is configured to transition the first switch between an ON state and an OFF state.

10. The switch assembly of claim 6 wherein the second switch comprises a second plurality of transistors, each transistor of the second plurality of transistors having a gate, a drain, and a source, the gate of each transistor of the second plurality of transistors being coupled to the second control node.

11. The switch assembly of claim 10 wherein the common resistor comprises a plurality of resistive elements arranged in series.

12. The switch assembly of claim 11 wherein at least one of the plurality of resistive elements of the common resistor is coupled between a drain and a source of a transistor of the second plurality of transistors.

13. The switch assembly of claim 11 wherein a resistive element of the plurality of resistive elements is coupled between a drain and a source of each transistor of the second plurality of transistors.

14. The switch assembly of claim 10 wherein the second switch further comprises a second plurality of gate resistors, each gate resistor of the second plurality of gate resistors coupled between a respective gate of the second plurality of transistors and the second control node.

15. The switch assembly of claim 14 wherein the second switch further comprises a second common resistor coupled between the second control node and each of the second plurality of gate resistors.

16. The switch assembly of claim 10 wherein the first plurality of transistors and/or the second plurality of transistors are metal oxide semiconductor field effect transistors.

17. The switch assembly of claim 10 wherein the first switch further comprises a first plurality of gate resistors, each gate resistor of the first plurality of gate resistors coupled between a respective gate of the first plurality of transistors and the common node.

18. The switch assembly of claim 2 wherein the first switch further comprises a plurality of drain-source resistors, each drain-source resistor being coupled between the drain and source of a corresponding transistor of the first plurality of transistors.

19. The switch assembly of claim 2 further comprising a resistor-capacitor filter coupled between the first control node and the second switch.

20. A method of designing a switch assembly for a radio frequency signal, the method comprising:

arranging a first switch having a first plurality of transistors coupled between a first node and a second node, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to a common node, the first node coupled to an input of the switch assembly, and the second node coupled to an output of the switch assembly;

arranging a common resistor coupled between a first control node and the common node, and arranging a second switch coupled between the first control node and the common node in parallel to the common resistor;

arranging a voltage level shifter coupled between the first control node and the second switch, the voltage level shifter configured to output a positive voltage and a negative voltage;

arranging a control resistor to be coupled between the first control node and the second switch;

controlling the second switch to be in an ON state such that a first control signal received by the first control node bypasses the common resistor between the first control node and the common node during a period in which the first switch is transitioning between an ON state and an OFF state; and

controlling the second switch to be in an OFF state such that the first control signal is communicated to the common node via the common resistor during a period in which the first switch is not transitioning between an ON state and an OFF state.