Low power single phase logic gate latch for clock-gating
Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.
1. A latch comprising:
a pair of cross-coupled transistor stacks comprising a first transistor stack and a second transistor stack;
a first clocked transistor coupled between the first transistor stack and the second transistor stack;
a second clocked transistor coupled to a common point of the first transistor stack and the second transistor stack;
a first input port configured to receive an enable signal; and
a clock port configured to receive an input clock signal, wherein the input clock signal is coupled to a gate of the first clocked transistor and to a gate of the second clocked transistor;
wherein the latch is configured to set an output data signal based on an input data signal and the input clock signal, wherein a value of the input data signal is based at least in part on a value of the enable signal.
2. The latch as recited in claim 1 , further comprising a second input port configured to receive the input data signal, wherein the input data signal is coupled to the first transistor stack.
3. The latch as recited in claim 2 , wherein the input data signal is coupled to a gate of a first P-type transistor of the first transistor stack, and wherein the input data signal is coupled to a gate of a first N-type transistor of the first transistor stack.
4. The latch as recited in claim 2 , wherein an inverted version of the input data signal is coupled to the second transistor stack.
5. The latch as recited in claim 4 , the inverted version of the input data signal is coupled to a gate of a first P-type transistor of the second transistor stack, and wherein the inverted version of the input data signal is coupled to a gate of a first N-type transistor of the second transistor stack.
6. The latch as recited in claim 2 , wherein;
the first clocked transistor is a P-type transistor coupled between the first transistor stack and the second transistor stack; and
the second clocked transistor is a first N-type transistor coupled to a source gate of a second N-type transistor of the first transistor stack gated by the input data signal and to a source gate of a third N-type transistor of the second transistor stack gated by an inverted version of the input data signal.
7. The latch as recited in claim 1 , further comprising a total of two clocked transistors that includes the first clocked transistor and the second clocked transistor.
8. A method comprising:
receiving an enable signal by an input port of a latch;
receiving, by a latch, an input data signal on gates of a first P-type transistor and a first N-type transistor of a first transistor stack, wherein a value of the input data signal is based at least in part on a value of the enable signal;
receiving an inverted version of the input data signal on gates of a second P-type transistor and a second N-type transistor of a second transistor stack, wherein the first transistor stack is cross-coupled to the second transistor stack;
receiving an input clock signal at a P-type clocked transistor coupled between the first transistor stack and the second transistor stack;
receiving the input clock signal at an N-type clocked transistor connected to a common point of the cross-coupled first and second transistor stacks; and
generating an output data signal by inverting an internal node of the cross-coupled first and second transistor stack.
9. The method as recited in claim 8 , wherein the P-type clocked transistor is coupled to a drain port of the first P-type transistor of the first transistor stack.
10. The method as recited in claim 9 , wherein the P-type clocked transistor is coupled to a drain port of the second P-type transistor of the second transistor stack.
11. The method as recited in claim 10 , wherein a drain port of the N-type clocked transistor is coupled to:
a source port of the first N-type transistor of the first transistor stack; and
a source port of the second N-type transistor of the second transistor stack.
12. The method as recited in claim 11 , further comprising receiving the input clock signal by a total of two clocked transistors that includes the N-type clocked transistor and the P-type clocked transistor.
13. The method as recited in claim 11 , wherein a source port of the N-type clocked transistor is coupled to ground.
14. The method as recited in claim 13 , wherein the drain port of the first P-type transistor of the first transistor stack is coupled to a third P-type transistor of the first transistor stack, and wherein the drain port of the second P-type transistor of the second transistor stack is coupled to a fourth P-type transistor of the second transistor stack.
15. An apparatus comprising:
an input port configured to receive an enable signal;
a data port configured to receive an input data signal, wherein a value of the input data signal is based at least in part on a value of the enable signal;
a clock port configured to receive a clock signal;
a first transistor stack connected between a supply voltage and ground;
a second transistor stack connected between the supply voltage and ground;
an N-type clocked transistor configured to receive the clock signal from the clock port, wherein the N-type clocked transistor is coupled to a common point of both the first transistor stack and the second transistor stack; and
a P-type clocked transistor configured to receive the clock signal from the clock port, wherein the P-type clocked transistor is coupled between the first transistor stack and the second transistor stack;
wherein the apparatus is configured to generate an output data signal from the input data signal based on a first inverter coupled to the first and second transistor stacks.
16. The apparatus as recited in claim 15 , wherein the input data signal is coupled to a gate of a first P-type transistor of the first transistor stack.
17. The apparatus as recited in claim 16 , further comprising a second inverter, wherein:
the input data signal is coupled to a gate of a first N-type transistor of the first transistor stack; and
the input data signal is coupled to the second inverter.
18. The apparatus as recited in claim 17 15 , further comprising a total of two clocked transistors that includes the N-type clocked transistor and the P-type clocked transistor.
19. The apparatus as recited in claim 17 , wherein an output of the second inverter is coupled to a gate of a second P-type transistor of the second transistor stack, and wherein the output of the second inverter is coupled to a gate of a second N-type transistor of the second transistor stack.
20. The apparatus as recited in claim 19 , wherein the N-type clocked transistor is coupled to a source port of the first N-type transistor of the first transistor stack and to a source port of the second N-type transistor of the second transistor stack, and wherein the P-type clocked transistor is coupled between a drain port of the first P-type transistor of the first transistor stack and a drain port of the second P-type transistor of the second transistor stack.