IP Library › Granted Patent US 12,160,492
Granted Patent B2
US 12,160,492 · App. 18/374,475 · Granted Dec 3, 2024

Device-to-device link training

Inventor: Kent C. Lusted (Aloha, OR)
Assignee: Intel Corporation
H04L69/24H04L49/3054H04L49/351H04L69/324
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Quick Facts
Patent No.
US 12,160,492
App. No.
18/374,475
Granted
Dec 3, 2024
Kind
B2
Abstract

Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

Claims (75)

1. An apparatus comprising:

a network interface device comprising:

a media access control (MAC) circuitry;

a direct memory access (DMA) circuitry; and

a physical layer interface (PHY) comprising:

circuitry to:

during link training of at least one lane with a remote link partner:

change from a TRAIN_LOCAL state to a TIMEOUT state based at least on expiration of a wait time,

enter a state based at least on loss of local_tf_lock state or loss of remote_tf_lock state, and

exit from the TIMEOUT state to a TRAINING_FAILED state based at least on a holdoff_timer_done state.

2. The apparatus of claim 1 , comprising:

circuitry to provide multiple transmit lanes;

analog equalizer circuitry associated with the multiple transmit lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple transmit lanes based on the link training.

3. The apparatus of claim 1 , comprising:

circuitry to provide multiple receive lanes;

analog equalizer circuitry associated with the multiple receive lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple receive lanes based on the link training.

4. The apparatus of claim 1 , wherein the local_tf_lock state comprises indication of successful decoding of training frames.

5. The apparatus of claim 1 , wherein the remote_tf_lock state comprises indication of successful decoding of training frames by the remote link partner.

6. The apparatus of claim 1 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state via an out-of-band communication.

7. The apparatus of claim 1 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state by a read of a register of the remote link partner.

8. The apparatus of claim 1 , wherein the link training is to commence based on connection of a cable.

9. The apparatus of claim 1 , wherein lane rates comprise 50 Gbps or 100 Gbps.

10. The apparatus of claim 1 , wherein at least one packet transmitted to the remote link partner is consistent with Ethernet.

11. An apparatus comprising:

a switch comprising:

circuitry to:

during link training of at least one lane with a remote link partner:

change from a TRAIN_LOCAL state to a TIMEOUT state based at least on expiration of a wait time,

enter a state based at least on loss of local_tf_lock state or loss of remote_tf_lock state, and

exit from the TIMEOUT state to a TRAINING_FAILED state based at least on a holdoff_timer_done state.

12. The apparatus of claim 11 , comprising:

circuitry to provide multiple transmit lanes;

analog equalizer circuitry associated with the multiple transmit lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple transmit lanes based on the link training.

13. The apparatus of claim 11 , comprising:

circuitry to provide multiple receive lanes;

analog equalizer circuitry associated with the multiple receive lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple receive lanes based on the link training.

14. The apparatus of claim 11 , wherein the local_tf_lock state comprises indication of successful decoding of training frames.

15. The apparatus of claim 11 , wherein the remote_tf_lock state comprises indication of successful decoding of training frames by the remote link partner.

16. The apparatus of claim 11 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state via an out-of-band communication.

17. The apparatus of claim 11 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state by a read of a register of the remote link partner.

18. The apparatus of claim 11 , wherein the link training is to commence based on connection of a cable.

19. The apparatus of claim 11 , wherein lane rates comprise 50 Gbps or 100 Gbps.

20. The apparatus of claim 11 , wherein at least one packet transmitted to the remote link partner is consistent with Ethernet.

21. An apparatus comprising:

Ethernet physical layer transceiver (PHY) circuitry for use in frame communication with a remote link partner, the Ethernet PHY circuitry comprising:

circuitry to:

during link training of at least one lane with a remote link partner:

change from a TRAIN_LOCAL state to a TIMEOUT state based at least on expiration of a wait time,

enter a state based at least on loss of local_tf_lock state or loss of remote_tf_lock state, and

exit from the TIMEOUT state to a TRAINING_FAILED state based at least on a holdoff_timer_done state.

22. The apparatus of claim 21 , comprising:

circuitry to provide multiple transmit lanes;

analog equalizer circuitry associated with the multiple transmit lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple transmit lanes based on the link training.

23. The apparatus of claim 21 , comprising:

circuitry to provide multiple receive lanes;

analog equalizer circuitry associated with the multiple receive lanes; and

a single microcontroller to control settings of the analog equalizer circuitry for the multiple receive lanes based on the link training.

24. The apparatus of claim 21 , wherein the local_tf_lock state comprises indication of successful decoding of training frames.

25. The apparatus of claim 21 , wherein the remote_tf_lock state comprises indication of successful decoding of training frames by the remote link partner.

26. The apparatus of claim 21 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state via an out-of-band communication.

27. The apparatus of claim 21 , wherein the circuitry is to:

receive communication of loss of remote_tf_lock state by a read of a register of the remote link partner.

28. The apparatus of claim 21 , wherein the link training is to commence based on connection of a cable.

29. The apparatus of claim 21 , wherein lane rates comprise 50 Gbps or 100 Gbps.

30. The apparatus of claim 21 , wherein at least one packet transmitted to the remote link partner is consistent with Ethernet.

Continuity (2)
Continuation 16859689 · Apr 27, 2020
Related Publication 20240064216A1 · Feb 22, 2024