IP Library › Granted Patent US 12,163,831
Granted Patent B2
US 12,163,831 · App. 18/568,420 · Granted Dec 10, 2024

APD bias circuit with dual analog feedback loop control

Inventors: Haimin Tao (Eindhoven, NL); Christian Jordan (Venlo, NL); Aleksandar Sevo (Eindhoven, NL); Karnekumar Arulandu (Breda, NL)
Assignee: SIGNIFY HOLDING B.V.
G01J1/44G01K7/22G01J2001/444G01J2001/4466
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Quick Facts
Patent No.
US 12,163,831
App. No.
18/568,420
Granted
Dec 10, 2024
Kind
B2
Abstract

A bias circuit ( 100 ) of an avalanche photodiode, APD, comprising: a voltage conversion module ( 110 ) connected to the APD, wherein the voltage conversion module ( 110 ) is configured to convert an input supply voltage (Vin) to a bias voltage for the APD; an error amplifier ( 120 ) connected to the voltage conversion module ( 110 ) for implementing a feedback control; a voltage feedback loop ( 130 ) configured to provide the error amplifier ( 120 ) a first analog signal related to the bias voltage; and a current feedback loop ( 140 ) configured to provide the error amplifier ( 120 ) a second analog signal related to the APD current; wherein the error amplifier ( 120 ) is configured to control the voltage conversion module ( 110 ) based on the first and the second analog signals.

Claims (21)

1. A bias circuit of an avalanche photodiode, APD, comprising:

a voltage conversion module connected to the APD, wherein the voltage conversion module is configured to convert an input supply voltage to a bias voltage for the APD;

an error amplifier connected to the voltage conversion module for implementing a feedback control;

a voltage feedback loop configured to provide the error amplifier a first analog signal related to the bias voltage; and

a current feedback loop configured to provide the error amplifier a second analog signal related to an APD current;

wherein the first analog signal and the second analog signal are provided to the error amplifier via a feedback node and the error amplifier is configured to control the voltage conversion module based on the first and the second analog signals.

2. The bias circuit according to claim 1 , wherein the error amplifier comprises an operational amplifier configured to compare a feedback signal according to either the first analog signal or the second analog signal against a reference, and wherein the comparison result is integrated and used to control the voltage conversion module.

3. The bias circuit according to claim 1 , wherein the first analog signal is captured via a voltage divider connected to an output node of the voltage conversion module.

4. The bias circuit according to claim 1 , wherein the second analog signal is captured via a current sensing resistor Rs connected to the APD in series.

5. The bias circuit according to claim 4 , wherein a capacitor is connected in parallel to the resistor Rs to bypass high frequency signals, thus creating an AC ground.

6. The bias circuit according to claim 1 , wherein the first analog signal is connected to the feedback node via a diode.

7. The bias circuit according to claim 1 , wherein the second analog signal is connected to the feedback node via an emitter follower.

8. The bias circuit according to claim 1 , the bias circuit further comprising a temperature sensing element for compensating a temperature dependence of a required bias voltage for achieving a certain gain level of the APD.

9. The bias circuit according to claim 8 , wherein the temperature sensing element is a NTC thermistor, which is configured to form a series circuit with a tuning resistor, wherein the series circuit is connected to the feedback node of the error amplifier.

10. The bias circuit according to claim 1 , the bias circuit further comprising an RC filter connected between the voltage conversion module and the APD.

11. The bias circuit according to claim 10 , the bias circuit further configured to provide a bias to more than one APD, wherein the voltage conversion module is connected to each APD via an RC filter, and the more than one RC filter is constructed by:

connecting an output of the voltage conversion module to the more than one APD via more than one cathode resistor, with each APD connected to an individual cathode resistor;

connecting a first capacitor between ground and a first node between a first cathode resistor and a corresponding first APD; and

connecting a further capacitor between the first node and a further node between a further cathode resistor and a corresponding further APD.

12. The bias circuit according to claim 1 , wherein the voltage conversion module comprises more than one up-conversion stage, and the voltage feedback loop is obtained from an intermediate up-conversion stage.

13. The bias circuit according to claim 1 , wherein the voltage conversion module comprises a boost converter as a first stage and a voltage multiplier connected to the boost converter as a further stage, and the first analog signal is captured via a voltage divider connected to an output node of the boost converter instead of the output node of the voltage conversion module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2023
From: TAO, HAIMIN; JORDAN, CHRISTIAN; SEVO, ALEKSANDER; ARULANDU, KARNEKUMAR
To: SIGNIFY HOLDING B.V.
Reel/Frame 065827/0231 →
Priority Claims (2)
EP 21178940 · Jun 11, 2021 · regional
EP 21185190 · Jul 13, 2021 · regional
Continuity (1)
Related Publication 20240271998A1 · Aug 15, 2024