Apparatus and methods for setting indicator data to indicate whether a group of contiguously addressed information entries in a selected address information table provides a base address indicating a location within a contiguously address region comprising multiple address information tables at a later table level

1. An apparatus comprising:

address processing circuitry to detect information relating to an input memory address by reference to a respective chain of information entries provided by address information tables in respective ones of an ordered plurality of hierarchical table levels;

the address processing circuitry being configured to select an address information table at a given table level according to a base address dependent upon an earlier information entry in an address information table earlier than the given table level in the ordered plurality of table levels; and

the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component dependent upon at least a portion of the input memory address applicable to the given table level, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries;

the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information tables at a later table level, wherein the address processing circuitry includes hardware circuitry.

2. The apparatus of claim 1 , in which a last information entry in the chain of information entries, provided by an address information table at a last table level in the ordered plurality of hierarchical table levels, defines the information relating to the input memory address.

3. The apparatus of claim 1 , in which the address processing circuitry comprises address translation circuitry to perform address translations, in which the information relating to the input memory address defines at least an address translation between that input memory address in an input address space and a translated output memory address in an output address space.

4. The apparatus of claim 3 , in which:

the input memory address is one of a virtual memory address and an intermediate physical address; and

the output memory address is one of an intermediate physical address and a physical address.

5. The apparatus of claim 1 , in which the address processing circuitry comprises permission circuitry, in which the information relating to an input memory address defines at least an access permission associated with the input memory address.

6. The apparatus of claim 1 , in which the indicator data is configured to indicate whether the group of one or more contiguous table entries in the selected address information table provide respective base addresses indicating a group of contiguously addressed address information tables at a next table level in the ordered plurality of hierarchical table levels.

7. The apparatus of claim 6 , comprising:

a cache memory to store data representing information entries retrieved from the address information tables by the address processing circuitry;

in which the cache memory is configured to store data representing a single base address in respect of a group of one or more contiguously addressed information entries for which the indicator data is detected to be set.

8. The apparatus of claim 1 , in which the indicator data is configured to indicate whether an information entry in the selected address information table provides a base address indicating a contiguously addressed region comprising multiple address information tables at a table level after a next table level in the ordered plurality of hierarchical table levels.

9. The apparatus of claim 8 , in which the address processing circuitry is configured to select, in response to accessing an information entry in the selected table level for which the indicator data is set, an information entry in an address information table at a table level after the next table level following the given level in the ordered plurality of hierarchical table levels.

10. The apparatus of claim 9 , in which the address processing circuitry is configured to select the information entry in an address information table at a table level after the next table level following the given level according to an offset component dependent upon at least respective portions of the input memory address associated with the given table level and the table level following the given table level.

11. A method comprising:

detecting information relating to an input memory address by reference to a respective chain of information entries provided by address information tables in an ordered plurality of hierarchical table levels;

selecting, for a given address information table at a given table level, an information entry in an address information table at a table level later than the given level in the ordered plurality of hierarchical table levels by a pointer defined by a base address dependent upon an information entry in the given address information table and an offset component dependent upon at least a portion of the input memory address, the pointer being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries; and

detecting whether indicator data is set to indicate whether a set of one or more contiguous table entries in the given address information table provide a base address specifying a contiguously addressed region comprising multiple address information tables at a later table level.

12. A method comprising:

generating information relating to input memory addresses;

generating address information tables in an ordered plurality of hierarchical table levels to provide the information relating to input memory addresses in which, for a given address information table at a given table level, an address information table at a given table level being selectable by a base address dependent upon an earlier information entry in an address information table earlier than the given table level in the ordered plurality of table levels and an information entry in a selected address information table being selectable according to an offset component dependent upon at least a portion of the input memory address applicable to the given table level, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information, the generating address information tables comprising:

detecting an amount of memory available to store the ordered plurality of hierarchical table levels to provide the information relating to input memory addresses;

detecting whether, in the detected amount of memory, a set of multiple address information tables at a same table level can be stored in a contiguously addressed memory region; and

when the set of multiple address information tables at the same table level can be stored in the contiguously addressed memory region, generating a set of one or more contiguous table entries in a higher table level to provide a base address specifying the contiguously addressed region; and

storing the address information tables to the memory.

13. An apparatus comprising:

processor circuitry to generate information relating to input memory addresses and to generate address information tables in an ordered plurality of hierarchical table levels to provide the information relating to input memory addresses in which, for a given address information table at a given table level, an address information table at a given table level being selectable by a base address dependent upon an earlier information entry in an address information table earlier than the given table level in the ordered plurality of table levels and an information entry in a selected address information table being selectable according to an offset component dependent upon at least a portion of the input memory address applicable to the given table level, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information;

the processor circuitry being configured to detect an amount of memory available to store the ordered plurality of hierarchical table levels to provide the information relating to input memory addresses and to detect whether, in the detected amount of memory, a set of multiple address information tables at a same table level can be stored in a contiguously addressed memory region; and when the set of multiple address information tables at the same table level can be stored in the contiguously addressed memory region, to generate a set of one or more contiguous table entries in a higher table level to provide a base address specifying the contiguously addressed region; and

a memory to store the address information tables, wherein the processor circuitry includes hardware circuitry.

14. A non-transitory computer readable medium comprising a computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising:

address processing circuitry to detect information relating to an input memory address by reference to a respective chain of information entries provided by address information tables in respective ones of an ordered plurality of hierarchical table levels;

the address processing circuitry being configured to select an address information table at a given table level according to a base address dependent upon an earlier information entry in an address information table earlier than the given table level in the ordered plurality of table levels; and

the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component dependent upon at least a portion of the input memory address applicable to the given table level, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries;

the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information tables at a later table level.