Accelerating predicated instruction execution in vector processors
Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.
1. A method for processing a vector by a system, employing a vector processor, comprising:
receiving, by a scheduler, predicated instructions; and
executing the predicated instructions, wherein the executing of a first predicated instruction of the predicated instructions comprises:
compressing elements in a first vector of the first predicated instruction, based on a comparison of a level of sparsity of a predicate of the first predicated instruction to a threshold that is based on a ratio of a number of elements in a hardware vector for executing the first predicated instruction and a number of elements in the first vector of the first predicated instruction, to generate compressed elements that are contiguously mapped as a second vector,
processing, by an execution unit, the compressed elements to generate processed compressed elements, and
decompressing the processed compressed elements.
2. The method of claim 1 , wherein the processing of the compressed elements is performed in one or more cycles, wherein the processing in a cycle of the one or more cycles comprises:
dispatching a subset of the compressed elements to the hardware vector of the execution unit; and
processing each of the elements in the dispatched subset by a corresponding SIMD lane of a first plurality of SIMD lanes of the execution unit according to an opcode of the first predicated instruction.
3. The method of claim 2 , wherein:
the dispatching comprises,
dispatching the subset of the compressed elements to a portion of the hardware vector, and
dispatching other vector elements to another portion of the hardware vector; and
the executing comprises,
processing the other vector elements by a second plurality of SIMD lanes of the execution unit according to the opcode.
4. The method of claim 1 , further comprising:
for a second predicated instruction of the predicated instructions, determining that compression should not occur.
5. The method of claim 1 , further comprising determining that compression should occur in response to the level of sparsity being above the threshold.
6. The method of claim 5 , wherein the determining is based on a user parameter, a configuration parameter associated with the system, or a combination thereof.
7. The method of claim 5 , wherein the determining is based on a number of the predicated instructions that are queued by the scheduler.
8. The method of claim 1 , wherein:
executing the first predicated instruction is performed speculatively.
9. A system, employing a vector processor, for processing a vector, comprising:
at least one processor; and
memory storing instructions that, when executed by the at least one processor, cause the at least one processor to:
receive, by a scheduler, predicated instructions, and
execute the predicated instructions, wherein to execute a first predicated instruction of the predicated instructions, the instructions stored in the memory further cause the at least one processor to:
compress, by a compressor, elements in a first vector of the first predicated instruction, based on a comparison of a level of sparsity of a predicate of the first predicated instruction to a threshold that is based on a ratio of a number of elements in a hardware vector for executing the first predicated instruction and a number of elements in the first vector of the first predicated instruction, to generate compressed elements that are contiguously mapped as a second vector,
process, by an execution unit, the compressed elements to generate processed compressed elements, and
decompress the processed compressed elements.
10. The system of claim 9 , wherein the processing of the compressed elements is performed in one or more cycles, wherein the processing in a cycle of the one or more cycles comprises:
dispatching a subset of the compressed elements to the hardware vector of the execution unit; and
processing each of the elements in the dispatched subset by a corresponding SIMD lane of a first plurality of SIMD lanes of the execution unit according to an opcode of the first predicated instruction.
11. The system of claim 10 , wherein:
the dispatching comprises,
dispatching the subset of the compressed elements to a portion of the hardware vector, and
dispatching other vector elements to another portion of the hardware vector; and
the executing comprises,
processing the other vector elements by a second plurality of SIMD lanes of the execution unit according to the opcode.
12. The system of claim 9 , wherein the instructions stored in the memory further cause the processor to:
for a second predicated instruction of the predicated instructions, determine that compression should not occur.
13. The system of claim 9 , wherein the instructions stored in the memory further cause the processor to determine that compression should occur in response to the level of sparsity being above the threshold.
14. The system of claim 13 , wherein the determining is based on a user parameter, a configuration parameter associated with the system, or a combination thereof.
15. The system of claim 13 , wherein the determining is based on a number of the predicated instructions that are queued by the scheduler.
16. A non-transitory computer-readable medium comprising instructions executable by at least one processor to perform a method for processing a vector by a system, employing a vector processor, the method comprising:
receiving, by a scheduler, predicated instructions; and
executing the predicated instructions, wherein the executing of a first predicated instruction of the predicated instructions comprises:
compressing elements in a first vector of the first predicated instruction, based on a comparison of a level of sparsity of a predicate of the first predicated instruction to a threshold that is based on a ratio of a number of elements in a hardware vector for executing the first predicated instruction and a number of elements in the first vector of the first predicated instruction, to generate compressed elements that are contiguously mapped as a second vector,
processing, by an execution unit, the mapped elements in the second vector, generating processed mapped elements, and
decompressing, by a decompressor, the processed mapped elements.
17. The non-transitory computer-readable medium of claim 16 , wherein the method further comprises:
for a second predicated instruction of the predicated instructions, determining that compression should not occur.
18. The non-transitory computer-readable medium of claim 16 , wherein the processing of the compressed elements is performed in one or more cycles, wherein the processing in a cycle of the one or more cycles comprises:
dispatching a subset of the compressed elements to the hardware vector of the execution unit; and
processing each of the elements in the dispatched subset by a corresponding SIMD lane of a first plurality of SIMD lanes of the execution unit according to an opcode of the first predicated instruction.