Semiconductor structure with buried power rail, integrated circuit and method for manufacturing the semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a fin and a dummy fin over a well region on the substrate, wherein the fin and the dummy fin are parallel with a first direction, and the dummy fin is wider than the fin;
forming a shallow trench isolation (STI) region over the substrate, wherein the fin and the dummy fin are separated from each other by the STI;
removing the dummy fin to form a trench in the STI region;
using the trench to form a power rail over the well region;
forming a doping region on the fin; and
forming a source contact over the power rail extending between the doping region and the power rail,
wherein the doping region is electrically connected to the power rail through the source contact,
wherein the source contact is laterally separated from the STI region by a blocking layer on sidewalls of the source contact,
wherein the source contact has a bottom surface in direct contact with the STI region.
2. The method as claimed in claim 1 , wherein the step of using the trench to form the power rail further comprises:
filling the trench with conducting material;
recessing the conducting material to a specific height; and
using the conducting material remaining after the recessing to form the power rail.
3. The method as claimed in claim 1 , wherein the power rail is disposed below the doping region.
4. The method as claimed in claim 1 , wherein the well region is a Ptype well region, and the doping region is an N-type doping region, and the doping region forms a source region of an NMOS transistor corresponding to the fin.
5. The method as claimed in claim 1 , wherein the well region is an Ntype well region, and the doping region is a P-type doping region, and the doping region forms a source region of a PMOS transistor corresponding to the fin.
6. The method as claimed in claim 1 , wherein when the well region is a P-type well region, the power rail is a VSS line, and when the well region is an N-type well region, the power rail is a VDD line.