Integrated circuits with recessed gate electrodes
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
1. An integrated circuit structure, comprising:
a gate electrode over a semiconductor channel region, the gate electrode comprising a bulk material having a bottom surface, a first side, a second side, and a top surface, and the gate electrode comprising a workfunction material along the bottom surface and partially along the first and second sides of the bulk material, the workfunction material having a top surface below the top surface of the bulk material;
a first dielectric spacer adjacent to a first side of the gate electrode;
a second dielectric spacer adjacent to a second side of the gate electrode, the second side opposite the first side; and
a high-k dielectric layer between the gate electrode and the semiconductor channel region, the high-k dielectric layer laterally between the first dielectric spacer and the portion of the workfunction material partially along the first side of the bulk material, and the high-k dielectric layer laterally between the second dielectric spacer and the portion of the workfunction material partially along the second side of the bulk material, wherein the high-k dielectric layer has a top surface above the top surface of the bulk material, the top surface of the high-k dielectric layer below a top surface of the first and second dielectric spacers.
2. The integrated circuit structure of claim 1 , wherein the semiconductor channel region is a semiconductor fin.
3. The integrated circuit structure of claim 1 , further comprising:
a first source or drain structure adjacent to the first dielectric spacer; and
a second source or drain structure adjacent to the second dielectric spacer.
4. The integrated circuit structure of claim 3 , further comprising:
a first conductive contact structure in direct contact with the first source or drain structure; and
a second conductive contact structure in direct contact with the second source or drain structure.
5. The integrated circuit structure of claim 1 , wherein high-k dielectric layer comprises hafnium and oxygen.
6. An integrated circuit structure, comprising:
a gate electrode over a semiconductor channel region, the gate electrode comprising a first material having a bottom surface, a first side, a second side, and a top surface, and the gate electrode comprising a second material along the bottom surface and partially along the first and second sides of the first material, the second material having a top surface below the top surface of the first material;
a first dielectric spacer adjacent to a first side of the gate electrode;
a second dielectric spacer adjacent to a second side of the gate electrode, the second side opposite the first side; and
a high-k dielectric layer between the gate electrode and the semiconductor channel region, the high-k dielectric layer laterally between the first dielectric spacer and the portion of the second material partially along the first side of the first material, and the high-k dielectric layer laterally between the second dielectric spacer and the portion of the second material partially along the second side of the first material, wherein the high-k dielectric layer has a top surface above the top surface of the first material, the top surface of the high-k dielectric layer below a top surface of the first and second dielectric spacers.
7. The integrated circuit structure of claim 6 , wherein the semiconductor channel region is a semiconductor fin.
8. The integrated circuit structure of claim 6 , further comprising:
a first source or drain structure adjacent to the first dielectric spacer; and
a second source or drain structure adjacent to the second dielectric spacer.
9. The integrated circuit structure of claim 8 , further comprising:
a first conductive contact structure in direct contact with the first source or drain structure; and
a second conductive contact structure in direct contact with the second source or drain structure.
10. The integrated circuit structure of claim 6 , wherein high-k dielectric layer comprises hafnium and oxygen.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a gate electrode over a semiconductor channel region, the gate electrode comprising a bulk material having a bottom surface, a first side, a second side, and a top surface, and the gate electrode comprising a workfunction material along the bottom surface and partially along the first and second sides of the bulk material, the workfunction material having a top surface below the top surface of the bulk material;
a first dielectric spacer adjacent to a first side of the gate electrode;
a second dielectric spacer adjacent to a second side of the gate electrode, the second side opposite the first side; and
a high-k dielectric layer between the gate electrode and the semiconductor channel region, the high-k dielectric layer laterally between the first dielectric spacer and the portion of the workfunction material partially along the first side of the bulk material, and the high-k dielectric layer laterally between the second dielectric spacer and the portion of the workfunction material partially along the second side of the bulk material, wherein the high-k dielectric layer has a top surface above the top surface of the bulk material, the top surface of the high-k dielectric layer below a top surface of the first and second dielectric spacers.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , further comprising:
a battery coupled to the board.
16. The computing device of claim 11 , further comprising:
a GPS coupled to the board.
17. The computing device of claim 11 , further comprising:
a compass coupled to the board.
18. The computing device of claim 11 , further comprising:
a speaker coupled to the board.
19. The computing device of claim 11 , further comprising:
a touchscreen display coupled to the board.
20. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.