Manufacturing method of package

1. A manufacturing method of a package, comprising

embedding contact vias in a semiconductor carrier, wherein the contact vias are electrically grounded;

providing a first die and a first encapsulant over the semiconductor carrier, wherein the first encapsulant encapsulates the first die;

forming first through insulating vias (TIV) aside the first die, wherein the first TIVs are electrically grounded through the contact vias;

grinding the first die, the first encapsulant, and the first TIVs; and

stacking a second die over the first die.

2. The method of claim 1 , further comprising:

forming an alignment layer over the semiconductor carrier, wherein the alignment layer comprises alignment marks.

3. The method of claim 2 , wherein the alignment marks are formed between and electrically connected to the contact vias and the first TIVs.

4. The method of claim 2 , further comprising:

forming a dielectric layer between the alignment layer and the first encapsulant, wherein the first TIVs penetrate through the dielectric layer.

5. The method of claim 1 , further comprising:

forming a first bonding layer over the first die, the first encapsulant, and the first TIVs; and

forming a second bonding layer over the second die, wherein the first bonding layer is hybrid bonded to the second bonding layer.

6. The method of claim 5 , further comprising:

encapsulating the second die and the second bonding layer by a second encapsulant; and

forming a carrier substrate over the second die and the second encapsulant.

7. The method of claim 1 , further comprising:

encapsulating the second die by a second encapsulant;

forming second TIVs aside the second die, wherein the second TIVs are electrically grounded through the first TIVs and the contact vias; and

grinding the second die, the second encapsulant, and the second TIVs.

8. The method of claim 7 , further comprising:

bonding a third die to the second die;

encapsulating the third die by a third encapsulant; and

forming a carrier substrate over the third die and the third encapsulant.

9. The method of claim 1 , wherein during the grinding of the first die, the first encapsulant, and the first TIVs, electrons generated from the grinding are travelled from a grinding surface to the contact vias through the first TIVs.

10. A manufacturing method of a package, comprising:

providing a semiconductor carrier having die regions and scribe line regions located between two adjacent die regions;

embedding contact vias in the scribe line regions of the semiconductor carrier, wherein the contact vias are electrically grounded;

placing first dies over the semiconductor carrier in the die regions;

encapsulating the first dies by a first encapsulant;

forming through insulating vias (TIV) over the semiconductor carrier in the scribe line regions, wherein the TIVs are electrically grounded through the contact vias;

grinding the first dies, the first encapsulant, and the TIVs;

stacking a second die over the first die; and

performing a singulation process to remove the TIVs located in the scribe line regions.

11. The method of claim 10 , further comprising:

forming a first bonding layer over the first die, the first encapsulant, and the TIVs; and

forming a second bonding layer over the second die, wherein the first bonding layer is hybrid bonded to the second bonding layer.

12. The method of claim 11 , further comprising:

encapsulating the second die and the second bonding layer by a second encapsulant; and

forming a carrier substrate over the second die and the second encapsulant.

13. The method of claim 10 , wherein each first die of the first dies comprises a semiconductor substrate, and the method further comprises:

removing a portion of the semiconductor substrate of each first die to form recesses; and

forming a protection layer to fill the recesses.

14. A manufacturing method of a package, comprising embedding contact vias in a semiconductor carrier, wherein the contact vias are electrically grounded;

providing a first die and a first encapsulant over the semiconductor carrier, wherein the first encapsulant encapsulates the first die;

forming first through insulating vias (TIV) penetrating through the first encapsulant, wherein the first TIVs are aligned with the contact vias and are electrically grounded through the contact vias;

grinding the first die, the first encapsulant, and the first TIVs to generate electrons on grinding surfaces of the first die, the first encapsulant, and the first TIVs;

allowing the electrons to travel through the first TIVs to reach the contact vias; and

stacking a second die over the first die.

15. The method of claim 14 , further comprising:

forming an alignment layer over the semiconductor carrier, wherein the alignment layer comprises alignment marks.

16. The method of claim 15 , wherein the alignment marks are formed between and electrically connected to the contact vias and the first TIVs.

17. The method of claim 15 , further comprising:

forming a dielectric layer between the alignment layer and the first encapsulant, wherein the first TIVs penetrate through the dielectric layer.

18. The method of claim 14 , further comprising:

forming a first bonding layer over the first die, the first encapsulant, and the first TIVs; and

forming a second bonding layer over the second die, wherein the first bonding layer is hybrid bonded to the second bonding layer.

19. The method of claim 18 , further comprising:

encapsulating the second die and the second bonding layer by a second encapsulant; and

forming a carrier substrate over the second die and the second encapsulant.

20. The method of claim 14 , wherein the method further comprises:

encapsulating the second die by a second encapsulant;

forming second TIVs penetrating through the second encapsulant, wherein the second TIVs are aligned with the first TIVs and are electrically grounded through the first TIVs and the contact vias;

grinding the second die, the second encapsulant, and the second TIVs to generate electrons on grinding surfaces of the second die, the second encapsulant, and the second TIVs; and

allowing the electrons to travel through the second TIVs and the first TIVs to reach the contact vias.