Packaged semiconductor devices including backside power rails and methods of forming the same

1. A method comprising:

forming a first integrated circuit device, wherein forming the first integrated circuit device comprises:

forming a first transistor structure on a first substrate;

forming a front-side interconnect structure over the first transistor structure; and

removing at least a portion of the first substrate to expose a first source/drain region of the first transistor structure;

forming a backside interconnect structure over the first transistor structure opposite the front-side interconnect structure, the backside interconnect structure comprising a first conductive feature electrically coupled to the first source/drain region of the first transistor structure; and

bonding a second integrated circuit device to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

2. The method of claim 1 , further comprising:

forming a first interconnect structure over a second transistor structure of the second integrated circuit device, the first interconnect structure being bonded to the front-side interconnect structure of the first integrated circuit device.

3. The method of claim 2 , wherein the first interconnect structure comprises a front-side power rail, and wherein the backside interconnect structure comprises a backside power rail electrically coupled to the first source/drain region of the first transistor structure through the first conductive feature.

4. The method of claim 2 , further comprising:

forming a second interconnect structure on a backside of the second transistor structure, wherein forming the second interconnect structure comprises:

forming a first dielectric layer on the backside of the second transistor structure; and

forming a first contact extending through the first dielectric layer to a source/drain region of the second transistor structure.

5. The method of claim 4 , wherein the backside interconnect structure comprises a first backside power rail electrically coupled to the first source/drain region of the first transistor structure through the first conductive feature, and wherein the second interconnect structure comprises a second backside power rail electrically coupled to the source/drain region of the second transistor structure through the first contact.

6. The method of claim 2 , wherein the first interconnect structure is on a backside of the second transistor structure.

7. The method of claim 6 , wherein the backside interconnect structure comprises a first backside power rail electrically coupled to the first source/drain region of the first transistor structure through the first conductive feature, and wherein the first interconnect structure comprises a second backside power rail electrically coupled to a source/drain region of the second transistor structure through a first contact.

8. A method comprising:

forming a first integrated circuit device, wherein forming the first integrated circuit device comprises:

forming a first transistor on a first substrate;

forming a front-side interconnect structure over the first transistor;

thinning the first substrate, wherein thinning exposes a first source/drain region of the first transistor;

forming a backside interconnect structure on the exposed first source/drain region, wherein forming the backside interconnect structure comprises:

forming a first dielectric layer over the first transistor;

forming a first backside via through the first dielectric layer and electrically coupled to the first source/drain region of the first transistor; and

forming a first conductive line electrically connected to the first backside via; and

forming a second integrated circuit device, wherein forming the second integrated circuit device comprises:

forming a second transistor on a second substrate; and

forming a first interconnect structure over the second transistor; and

bonding the first interconnect structure of the second integrated circuit device to the front-side interconnect structure of the first integrated circuit device, wherein bonding the first interconnect structure of the second integrated circuit device to the front-side interconnect structure of the first integrated circuit device comprises forming dielectric-to-dielectric bonds between the first interconnect structure and front-side interconnect structure.

9. The method of claim 8 , wherein forming the first interconnect structure comprises forming a second conductive line over and electrically coupled to the second transistor, wherein the first conductive line is a first power rail, and wherein the second conductive line is a second power rail.

10. The method of claim 8 , wherein forming the second integrated circuit device further comprises:

thinning the second substrate, wherein thinning exposes a second source/drain region of the second transistor, wherein forming the first interconnect structure comprises:

forming a second dielectric layer over the exposed second source/drain region;

forming a second backside via through the second dielectric layer and electrically coupled to the second source/drain region of the second transistor; and

forming a second conductive line electrically connected to the second backside via.

11. The method of claim 10 , wherein the first interconnect structure is on a backside of the second transistor.

12. The method of claim 10 , wherein the first interconnect structure is on a front-side of the second transistor.

13. The method of claim 10 , wherein forming the second integrated circuit device further comprises:

forming a second interconnect structure over the second transistor opposite the first interconnect structure.

14. The method of claim 13 further comprising:

forming a passivation layer on a surface of the second interconnect structure opposite the second transistor;

forming an underbump metallization (UBM) in the passivation layer; and

forming an external connector on the UBM, the external connector being electrically coupled to the second interconnect structure through the UBM.

15. The method of claim 8 , wherein the second integrated circuit device comprises a gate contact electrically coupled to a gate structure of the second transistor, wherein the first interconnect structure comprises a power rail over a front-side of the second transistor, the power rail being electrically coupled to the gate structure through the gate contact.

16. A device comprising:

a first integrated circuit device comprising:

a first device layer over a first substrate, the first device layer comprising a first transistor; and

a backside interconnect structure on the first device layer, the backside interconnect structure comprising a first power rail on a backside of the first device layer, the first power rail being electrically coupled to a first source/drain region of the first transistor through a first backside via; and

a second integrated circuit device comprising:

a second device layer over a second substrate, the second device layer comprising a second transistor; and

a first interconnect structure on the second device layer, wherein the first interconnect structure is bonded to the backside interconnect structure by dielectric-to-dielectric bonds.

17. The device of claim 16 , wherein the first interconnect structure comprises:

a first dielectric layer on a backside of the second device layer; and

a second power rail on the first dielectric layer, the second power rail being electrically coupled to a second source/drain region of the second transistor through a second backside via.

18. The device of claim 16 , wherein the first interconnect structure is on a front-side of the second device layer, wherein the second integrated circuit device further comprises a second interconnect structure on the second device layer, the second interconnect structure comprising a second power rail on a backside of the second device layer, the second power rail being electrically coupled to a second source/drain region of the second transistor through a second backside via.

19. The device of claim 18 , wherein the second integrated circuit device further comprises:

a passivation layer on a surface of the second interconnect structure opposite the second device layer;

an underbump metallization (UBM) in the passivation layer; and

an external connector on the UBM, the external connector being electrically coupled to the second interconnect structure through the UBM.

20. The device of claim 16 , wherein the first backside via is electrically coupled to the first source/drain region through a first silicide region.