Integrated circuit device with power control circuit having various transistor types and method

1. An integrated circuit (IC) device, comprising:

a power control circuit comprising a first transistor of a first type, and a second transistor of a second type different from the first type,

wherein

the first transistor comprises:

a gate terminal configured to receive a control signal,

a first terminal electrically coupled to a first power supply node, and

a second terminal electrically coupled to a second power supply node,

the second transistor comprises:

a gate terminal configured to receive the control signal, and

first and second terminals configured to receive a predetermined voltage, and

the first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.

2. The IC device of claim 1 , wherein

the predetermined voltage is one of

the control signal,

a first power supply voltage of the first power supply node,

a second power supply voltage of the second power supply node,

a third power supply voltage different from the first power supply voltage, or

a voltage other than the control signal and the first through third power supply voltages.

3. The IC device of claim 1 , wherein

the power control circuit is a header circuit,

the first transistor is a P-type transistor, and

the second transistor is an N-type transistor.

4. The IC device of claim 1 , wherein

the power control circuit is a footer circuit,

the first transistor is an N-type transistor, and

the second transistor is a P-type transistor.

5. The IC device of claim 1 , wherein

in response to the first transistor being in a turned OFF state, the first power supply node is disconnected from the second power supply node and is floating.

6. An integrated circuit (IC) device, comprising:

a first active region of a first semiconductor type;

a second active region of a second semiconductor type, the second semiconductor type different from the first semiconductor type;

a plurality of gate regions extending over and across the first and second active regions;

a plurality of contact structures over and in electrical contact with corresponding portions of the first and second active regions; and

a conductive layer over the plurality of gate regions and the plurality of contact structures, the conductive layer comprising:

a first conductive pattern electrically coupling a first set of the contact structures over the first active region together,

a second conductive pattern electrically coupling a second set of the contact structures over the first active region together, and

a third conductive pattern electrically coupling the first set of the contact structures over the first active region together.

7. The IC device of claim 6 , wherein

the plurality of gate regions and the first active region are configured as a first transistor of a first type, and

the plurality of gate regions and the second active region are configured as a second transistor of a second type different from the first type.

8. The IC device of claim 7 , wherein

the first conductive pattern is configured as a first power rail,

the second conductive pattern is configured as a second power rail,

the third conductive pattern is configured as a third power rail, and

the first transistor is configured to, in response to a control signal, connect or disconnect the first and third power rails to or from the second power rail.

9. The IC device of claim 8 , wherein

the conductive layer further comprises:

a fourth conductive pattern electrically coupling the plurality of gate regions together.

10. The IC device of claim 9 , wherein

the conductive layer further comprises:

a fifth conductive pattern electrically coupling the contact structures over the second active region together, and

the fourth conductive pattern and the fifth conductive pattern are electrically coupled together.

11. The IC device of claim 8 , wherein

the conductive layer further comprises:

a fourth conductive pattern electrically coupling the contact structures over the second active region together,

the fourth conductive pattern is either configured to receive a predetermined voltage, or configured as a third power rail, and

the predetermined voltage is a voltage other than all of

the control signal,

a first power supply voltage of the first power rail and the third power rail,

a second power supply voltage of the second power rail, and

a third power supply voltage different from the first power supply voltage, a functional circuit operable by the first power supply voltage and the third power supply voltage.

12. The IC device of claim 6 , wherein

the contact structures in the first set are arranged alternatingly with the contact structures in the second set along a first axis, and

the second conductive pattern is arranged between the first conductive pattern and the third conductive pattern along a second axis transverse to the first axis.

13. The IC device of claim 6 , wherein

the conductive layer further comprises:

a fourth conductive pattern electrically coupling the second set of the contact structures together.

14. The IC device of claim 13 , wherein

the contact structures in the first set are arranged alternatingly with the contact structures in the second set along a first axis, and

the second and fourth conductive patterns are arranged alternatingly with the first and third conductive patterns along a second axis transverse to the first axis.

15. The IC device of claim 13 , wherein

the contact structures of the second set extend continuously from the first active region to the second active region to form a corresponding set of the contact structures over the second active region.

16. The IC device of claim 6 , wherein

the contact structures of the first set extend continuously from the first active region to the second active region to form a corresponding set of the contact structures over the second active region.

17. The IC device of claim 6 , further comprising:

a third active region of the first semiconductor type;

a fourth active region of the second semiconductor type;

a plurality of further gate regions extending over and across the third and fourth active regions, the plurality of further gate regions correspondingly aligned with the plurality of gate regions; and

a plurality of further contact structures over and in electrical contact with corresponding portions of the third and fourth active regions,

wherein

the conductive layer further comprises:

a fourth conductive pattern electrically coupling a third set of the further contact structures over the third active region together,

a fifth conductive pattern electrically coupling a fourth set of the further contact structures over the third active region together, and

a sixth conductive pattern electrically coupling the third set of the further contact structures over the third active region together.

18. The IC device of claim 6 , wherein

the conductive layer is a metal zero (M0) layer.

19. A method, comprising:

forming, over a substrate, a first active region of a first semiconductor type and a second active region of a second semiconductor type different from the first semiconductor type, the first and second active regions extending along a first axis;

forming a gate structure over the first and second active regions, the gate structure extending continuously from the first active region to the second active region along a second axis transverse to the first axis, wherein

the gate structure and the first active region are configured as a first transistor of a first type, and

the gate structure and the second active region are configured as a second transistor of a second type different from the first type; and

depositing a conductive layer over the gate structure and the first and second active regions, and patterning the conductive layer into a plurality of conductive patterns extending along the first axis, the plurality of conductive patterns comprising:

a first conductive pattern electrically coupled to first and second terminals of the second transistor to form the second transistor as a dummy transistor.

20. The method of claim 19 , wherein

the plurality of conductive patterns further comprises:

a second conductive pattern electrically coupled to the gate structure, and the second conductive pattern is

over the second active region, or

over a space between the first and second active regions.