Complementary metal-oxide-semiconductor device and method of manufacturing the same

1. A manufacturing method of a complementary metal-oxide-semiconductor device, comprising:

forming semiconductor fins and fin bases over a semiconductor substrate, wherein the fin bases are protruded from the semiconductor substrate, and the semiconductor fins are continuously connected to the fin bases and extend parallel with respect to each other in a first direction;

forming nanosheets over the semiconductor fins;

forming a gate structure elongated along a second direction and extending along a third direction to laterally wrap around each of the nanosheets and laterally wrap around each of the semiconductor fins in a first cross-sectional view, wherein the first direction is substantially perpendicular to the second direction and the third direction; and

forming a common source/drain region wrapping around each of the nanosheets and extending to cover each of the semiconductor fins in a second cross-sectional view.

2. The manufacturing method of claim 1 , further comprising:

forming a common source/drain contact surrounding the common source/drain region.

3. The manufacturing method of claim 1 , further comprising:

forming a metal plug adjacent to the fin bases and vertically between the semiconductor substrate and the gate structure in the second cross-sectional view after forming the common source/drain region.

4. The manufacturing method of claim 3 , further comprising:

forming a lower source/drain region over the semiconductor substrate; and

forming a lower source/drain contact to couple the lower source/drain region, wherein after the metal plug is formed, the lower source/drain contact couples the lower source/drain region to the metal plug in a third-cross sectional view.

5. The manufacturing method of claim 4 , further comprising:

forming an upper source/drain region over the lower source/drain region; and

forming an upper source/drain contact surrounding the upper source/drain region and physically separated from the lower source/drain contact in the third-cross sectional view.

6. The manufacturing method of claim 1 , wherein a width of a first semiconductor fin of the semiconductor fins in the second direction is formed to be equal to a width of a first nanosheet of the nanosheets in the second direction.

7. The manufacturing method of claim 1 , wherein a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.

8. A manufacturing method of a complementary metal-oxide-semiconductor device, comprising:

forming semiconductor fins and nanosheets, wherein the nanosheets are formed over the semiconductor fins;

forming a gate structure to be in contact with each of the nanosheets and each of the semiconductor fins in a first view;

forming a common source/drain region to surround each of the nanosheets and each of the semiconductor fins in a second view different from the first view, wherein the common source/drain region comprises a first source/drain region and a second source/drain region, an upper portion of the first source/drain region surrounding a portion of the nanosheets is partially merged with and partially connected to an upper portion of the second source/drain region surrounding another portion of the nanosheets, and a lower portion of the first source/drain region surrounding one of the semiconductor fins and a lower portion of the second source/drain region surrounding another one of the semiconductor fins are merged.

9. The manufacturing method of claim 8 , wherein a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.

10. The manufacturing method of claim 8 , wherein forming the semiconductor fins comprises:

forming alternating stacked semiconductor layers of channel material and sacrificial material on a semiconductor substrate;

etching the stacked semiconductor layers of the channel material and the sacrificial material to form sacrificial fins;

removing the sacrificial fins to expose fin bases protruding from the semiconductor substrate; and

growing a semiconductor material of the semiconductor fins on the fin bases.

11. The manufacturing method of claim 10 , wherein the nanosheets are formed from the stacked semiconductor layers of the channel material and the sacrificial material on the semiconductor substrate and are formed together with the sacrificial fins.

12. The manufacturing method of claim 8 , wherein forming the gate structure comprises:

forming a dummy gate structure extending across the semiconductor fins and the nanosheets;

forming gate spacers at sides of the dummy gate structure;

removing the dummy gate structure to open a gate trench in between the gate spacers; and

forming gate materials in the gate trench.

13. The manufacturing method of claim 8 , further comprising:

forming a metal plug adjacent to a base of one of the semiconductor fins after forming the common source/drain region.

14. A manufacturing method of a complementary metal-oxide-semiconductor device, comprising:

forming a first semiconductor fin, a second semiconductor fin, first nanosheets over the first semiconductor fin, and second nanosheets over the second semiconductor fin, wherein forming the first and second semiconductor fins comprises:

forming alternating stacked semiconductor layers of channel material and sacrificial material on a semiconductor substrate;

etching the stacked semiconductor layers of channel material and sacrificial material to form sacrificial fins;

removing the sacrificial fins; and

growing a semiconductor material of the semiconductor fins after removing the sacrificial fins;

forming a gate structure to surround the first semiconductor fin, the second semiconductor fin, each of the first nanosheets, and each of the second nanosheets in a view; and

forming a first source/drain region and a second source/drain region, wherein the first source/drain region surrounds the first semiconductor fin and each of the first nanosheets, and the second source/drain region surrounds the second semiconductor fin and each of the second nanosheets in another view.

15. The manufacturing method of claim 14 , wherein after forming the first source/drain region and the second source/drain region, the first source/drain region and the second source/drain region are laterally connected to form a common source/drain region.

16. The manufacturing method of claim 14 , further comprising:

forming a source/drain contact to surround the first source/drain region and the second source/drain region.

17. The manufacturing method of claim 14 , wherein a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.

18. The manufacturing method of claim 14 , wherein forming the first semiconductor fin and the first nanosheets comprises:

forming the first nanosheets with a width to be equal to a width of the first semiconductor fin.

19. The manufacturing method of claim 14 , wherein after forming the first source/drain region and the second source/drain region, an upper portion of the first source/drain region is partially merged with an upper portion of the second source/drain region, and a lower portion of the first source/drain region and a lower portion of the second source/drain region surrounding another one of the semiconductor fins are merged.

20. The manufacturing method of claim 14 , wherein forming the gate structure comprises:

forming a dummy gate structure extending across the first semiconductor fin, the second semiconductor fin, the first nanosheets, and the second nanosheets;

forming gate spacers at sides of the dummy gate structure;

removing the dummy gate structure to open a gate trench in between the gate spacers; and

forming gate materials in the gate trench.