IP Library › Granted Patent US 12,166,088
Granted Patent B2
US 12,166,088 · App. 17/854,817 · Granted Dec 10, 2024

Source/drain contact structure

Inventors: Ting Fang (Hsinchu, TW); Chung-Hao Cai (Hsinchu, TW); Jui-Ping Lin (Hsinchu, TW); Chia-Hsien Yao (Hsinchu, TW); Chen-Ming Lee (Yangmei, TW); Fu-Kai Yang (Hsinchu, TW); Mei-Yun Wang (Hsin-Chu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/401H01L21/31144H01L21/32115H01L29/0665H01L29/41725H01L29/41791H01L29/785H01L2029/7858
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Quick Facts
Patent No.
US 12,166,088
App. No.
17/854,817
Granted
Dec 10, 2024
Kind
B2
Abstract

A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Claims (84)

1. A method, comprising:

receiving a workpiece comprising:

a gate structure disposed over a channel region of an active region,

a first gate spacer feature disposed along a first sidewall of the gate structure,

a second gate spacer feature disposed along a second sidewall of the gate structure, the second sidewall opposing the first sidewall,

a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature,

a first source/drain feature disposed over a first source/drain region of the active region,

a second source/drain feature disposed over a second source/drain region of the active region,

a first dielectric layer over the first source/drain feature, and

a second dielectric layer over the second source/drain feature;

forming a contact cut opening over the first source/drain feature while the second dielectric layer is masked, the contact cut opening displacing a top portion of the first dielectric layer;

depositing a hard mask layer over the workpiece and in the contact cut opening;

after the depositing of the hard mask layer, planarizing the workpiece until a top surface of the hard mask layer is coplanar with a top surface of the second dielectric layer;

forming a source/drain contact opening by removing the second dielectric layer to expose the second source/drain feature; and

forming a source/drain contact in the source/drain contact opening.

2. The method of claim 1 ,

wherein the first dielectric layer and the second dielectric layer comprise silicon oxide,

wherein the first gate spacer feature, and the second gate spacer feature, the gate-top dielectric feature, and the hard mask layer comprise silicon nitride.

3. The method of claim 1 , wherein, after the planarizing of the workpiece, the first source/drain feature underlies the hard mask layer and the first dielectric layer, and the second source/drain feature underlies the second dielectric layer.

4. The method of claim 1 , wherein the workpiece further comprises a contact etch stop layer (CESL) disposed between the first dielectric layer and the first source/drain feature and between the second dielectric layer and the second source/drain feature.

5. The method of claim 1 , wherein the channel region of the active region comprises a fin-like structure.

6. The method of claim 1 , wherein the channel region of the active region comprises a vertical stack of nanostructures and the gate structure wraps around each of the vertical stack of nanostructures.

7. The method of claim 1 , wherein a composition of the hard mask layer is different from a composition of the second dielectric layer.

8. The method of claim 1 , wherein, after the planarizing of the workpiece, the top surface of the hard mask layer is coplanar with a top surface of the gate-top dielectric feature.

9. The method of claim 1 , wherein the forming of the source/drain contact opening comprises:

depositing a top dielectric layer over the workpiece;

depositing a tungsten carbide layer over the top dielectric layer;

forming an access opening through the tungsten carbide layer, the access opening being over the hard mask layer and the second dielectric layer; and

selectively etching the second dielectric layer.

10. A method, comprising:

receiving a workpiece comprising:

a gate structure disposed over a channel region of an active region,

a first gate spacer feature disposed along a first sidewall of the gate structure,

a second gate spacer feature disposed along a second sidewall of the gate structure, the second sidewall opposing the first sidewall,

a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature,

a first source/drain feature disposed over a first source/drain region of the active region,

a second source/drain feature disposed over a second source/drain region of the active region,

a first dielectric layer over the first source/drain feature, and

a second dielectric layer over the second source/drain feature;

replacing a top portion of the first dielectric layer with a hard mask layer, wherein the hard mask layer spans at least an entire width of the first source/drain feature;

selectively etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature; and

after the selectively etching of the second dielectric layer, forming a source/drain contact over the second source/drain feature.

11. The method of claim 10 ,

wherein the first dielectric layer and the second dielectric layer comprise silicon oxide,

wherein the first gate spacer feature, and the second gate spacer feature, the gate-top dielectric feature, and the hard mask layer comprise silicon nitride.

12. The method of claim 10 , wherein the replacing comprises:

forming a contact cut opening over the first source/drain feature while the second dielectric layer is masked, the contact cut opening displacing the top portion of the first dielectric layer;

depositing the hard mask layer over the contact cut opening; and

planarizing the workpiece until a top surface of the hard mask layer is coplanar with a top surface of the second dielectric layer.

13. The method of claim 10 , wherein a composition of the hard mask layer is different from a composition of the second dielectric layer.

14. The method of claim 10 , wherein the forming of the source/drain contact comprises:

forming a silicide layer over the workpiece and on the second source/drain feature;

depositing a metal fill layer over the silicide layer; and

planarizing the workpiece until a top surface of the metal fill layer is coplanar with a top surface of the hard mask layer.

15. The method of claim 10 , wherein the selectively etching comprises:

depositing a top dielectric layer over the workpiece;

depositing a tungsten carbide layer over the top dielectric layer;

forming an access opening through the tungsten carbide layer, the access opening being over the hard mask layer and the second dielectric layer; and

selectively etching the second dielectric layer.

16. A method, comprising:

receiving a workpiece comprising:

a first source/drain feature over a first source/drain region,

a second source/drain feature over a second source/drain region,

a gate structure over a channel region disposed between the first and second source/drain regions,

a gate-top dielectric feature over the gate structure,

a first dielectric layer over the first source/drain feature, and

a second dielectric layer over the second source/drain feature;

selectively recessing a top portion of the first dielectric layer, wherein the selectively recessing includes forming a contact cut opening over the first source/drain feature while the second dielectric layer is masked, the contact cut opening displacing the top portion of the first dielectric layer;

depositing a hard mask layer over the first and second dielectric layers such that the hard mask layer fills the recessed top portion of the first dielectric layer;

planarizing the workpiece such that a top surface of the hard mask layer and a top surface of the second dielectric layer are coplanar;

depositing a third dielectric layer over the hard mask layer and the second dielectric layer;

forming an access opening partially through the third dielectric layer;

after the forming of the access opening, forming a source/drain contact opening through the second dielectric layer to expose the second source/drain feature; and

forming a source/drain contact in the source/drain contact opening.

17. The method of claim 16 , wherein the workpiece further comprises a first gate spacer along a sidewall of the first dielectric layer and a second gate spacer along a sidewall of the second dielectric layer, wherein the gate-top dielectric feature is further disposed over top and side surfaces of the first and second gate spacers.

18. The method of claim 16 , wherein the workpiece further comprises a contact etch stop layer (CESL) disposed between the first dielectric layer and the first source/drain feature and between the second dielectric layer and the second source/drain feature.

19. The method of claim 17 ,

wherein the first dielectric layer and the second dielectric layer comprise silicon oxide,

wherein the first gate spacer, and the second gate spacer, the gate-top dielectric feature, and the hard mask layer comprise silicon nitride.

20. The method of claim 17 , wherein the forming of the source/drain contact comprises:

depositing a metal liner over the workpiece;

forming a silicide layer over the workpiece and on the second source/drain feature;

depositing a metal fill layer over the silicide layer; and

planarizing the workpiece until a top surface of the metal fill layer is coplanar with the top surface of the hard mask layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER 17894862 PREVIOUSLY RECORDED AT REEL: 061559 FRAME: 0940. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Dec 30, 2022
From: FANG, TING; CAI, CHUNG-HAO; LIN, JUI-PING; YAO, CHIA-HSIEN; LEE, CHEN-MING; YANG, FU-KAI; WANG, MEI-YUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062252/0271 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2022
From: FANG, TING; CAI, CHUNG-HAO; LIN, JUI-PING; YAO, CHIA-HSIEN; LEE, CHEN-MING; YANG, FU-KAI; WANG, MEI-YUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 061559/0940 →
Continuity (2)
Division 16935686 · Jul 22, 2020
Related Publication 20220336592A1 · Oct 20, 2022