High precision multi-chip clock synchronization

1. A circuit, comprising:

a first integrated circuit (“IC”) and a second IC;

a delay loop comprising at least one transmission path between the first IC and the second IC for propagating a signal through the transmission path, during an initialization, and for calculating a propagation delay time, T latency , between the first IC and the second IC;

a synchronizing circuit on the second IC for recording a first time delay of an event relative to a second time delay of the event received at the first IC, comprising:

a phase-locked loop (PLL) circuit for generating a plurality of timing signals for the second IC using the PLL;

at least one time digitizer unit (TDU) for receiving a global offset, comprising global timing information and the T latency , and for generating a timestamp to represent the first time delay at the second IC associated with the event relative to the second time delay of the event at the first IC, the TDU comprising:

a counter for generating most significant bits for a count;

a circuit for receiving the PLL timing signals and for generating least significant bit (LSB) for the count, wherein the resolution of the LSB of the count is based on gate delay of the PLL circuit; and

at least one adder for adding the global offset and the count to generate the timestamp for the event.

2. The circuit as set forth in claim 1 , wherein a gate delay of the PLL comprises a least significant bit of less than or equal to 50 picoseconds for the timestamp.

3. The circuit as set forth in claim 2 , wherein the PLL comprises a phase-frequency detector, a charge pump, loop filter, M-stage ring oscillator, phase interpolator and divider circuits for phase locking at least one of the timing signals to a system reference clock.

4. The circuit as set forth in claim 1 , wherein the TDU further comprises:

a plurality of flip-flops and an encoder for receiving the timing signals from the PLL circuit and a strobe and for generating a plurality of bits of the timestamp.

5. The circuit as set forth in claim 4 , wherein: the flip-flops and the encoder further for generating a n bit binary representation for the timestamps.

6. The circuit as set forth in claim 1 , wherein the delay loop further comprises:

a first TDU and a transmitter, located on the first IC, a first transmission path between the first IC and a second IC, a loopback path in the second IC, a second transmission path between the second IC and the first IC, a receiver on the first IC and a second TDU on the first IC; and

datapath logic, located on the first IC, for propagating a signal in the delay loop and for calculating the propagation delay time, T latency , from the timestamps of the first and second TDUs.

7. The circuit as set forth in claim 1 , further comprising a plurality of the TDUs for generating a plurality of timestamps on the second IC.

8. A method for synchronizing two integrated circuits, comprising:

propagating a signal through a transmission path, during an initialization between the first IC and the second IC;

calculating a propagation delay time, T latency , between the first IC and the second IC;

recording a first time delay of an event relative to a second time delay of the event received at the first IC, by:

generating a plurality of timing signals for the second IC using a phase-locked loop (PLL);

receiving a global offset, comprising global timing information and the T latency ;

generating a timestamp at the second IC, in at least one time digitizer unit (TDU), so as to generate the timestamp of the event at the second IC relative to the second time delay of the event at the first IC, by:

generating most significant bits for a count;

receiving the PLL timing signals and for generating a least significant bit (LSB) for the count, wherein the resolution of the LSB of the count is based on gate delay of the PLL circuit; and

adding the global offset and the count to generate the timestamp for the event.

9. The method as set forth in claim 8 , wherein a gate delay of the PLL comprises a least significant bit of less than or equal to 50 picoseconds for the timestamp.

10. The method as set forth in claim 9 , wherein generating a plurality of timing signals comprises phase locking at least one of the timing signals to a system reference clock in the PLL that comprises a phase-frequency detector, a charge pump, loop filter, M-stage ring oscillator, phase interpolator and divider circuits.

11. The method as set forth in claim 8 , wherein the TDU further comprises:

a plurality of flip-flops and an encoder for receiving the timing signals from the PLL circuit and a strobe and for generating a plurality of bits of the timestamp.

12. The method as set forth in claim 11 , further comprising generating a n bit binary representation for the timestamps.

13. The method as set forth in claim 8 , wherein calculating a propagation delay time, T latency , between a first IC and a second IC further comprises:

propagating a signal, from the first IC, through a first TDU and a transmitter, located on the first IC, a first transmission path between the first IC and a second IC, a loopback path in the second IC, a second transmission path between the second IC and the first IC, a receiver on the first IC and a second TDU on the first IC; and

calculating the propagation delay time, T latency , from the timestamps of the first and second TDUs.

14. The method as set forth in claim 8 , further comprising generating a plurality of timestamps on the second IC from a plurality of the TDU.