Gate driving circuit and display device

1. A display device, comprising:

a display panel in which a plurality of subpixels is disposed;

a gate line electrically connected to at least one of the plurality of subpixels; and

a gate driving circuit outputting a gate signal to the gate line,

wherein the gate driving circuit comprising:

a pull-up transistor controlled by a voltage level of a Q node;

a pull-down transistor controlled by a voltage level of a QB node;

a pump capacitor electrically connected between the Q node and an input terminal of a gate clock signal; and

a pump transistor electrically connected between the pump capacitor and the Q node, and controlled by the gate signal output to the gate line,

wherein in a period that the pump transistor is turned-on, a difference between the voltage level of the Q node and a voltage level of a light-emitting control signal increases, and

wherein the gate signal is the light-emitting control signal.

2. The display device of claim 1 , wherein a gate node of the pump transistor is electrically connected to a node between the pump transistor and the pump capacitor.

3. The display device of claim 1 , wherein in a period that the pump transistor is turned-on, the voltage level of the Q node is maintained when a level of the gate clock signal is changed from a first level to a second level, and the voltage level of the Q node is changed when the level of the gate clock signal is changed from the second level to the first level.

4. The display device of claim 3 , wherein a gate node of the pump transistor is electrically connected to a node between the pump transistor and the pump capacitor, and the pump transistor is a P type transistor, and

wherein the second level is higher than the first level.

5. The display device of claim 3 , wherein in a period that the pump transistor is turned-on, a voltage level of the gate clock signal is changed several times.

6. The display device of claim 1 , wherein the pull-up transistor is a P type transistor, and in a period that the pump transistor is turned-on, the voltage level of the Q node is smaller than the voltage level turning-on the pull-up transistor.

7. The display device of claim 1 , wherein the gate driving circuit further comprising:

a feed transistor electrically connected between a gate node of the pump transistor and an input terminal of a first gate driving voltage, and controlled by a voltage level of the gate signal output to the gate line.

8. The display device of claim 7 , wherein a level of the first gate driving voltage is a level turning-on the pump transistor.

9. The display device of claim 1 , wherein the gate driving circuit further comprising:

a clock transistor electrically connected between the pump capacitor and the input terminal of the gate clock signal, and controlled by a voltage level of a gate start signal.

10. The display device of claim 9 , wherein a voltage level of the gate clock signal is changed several times in a period that the voltage level of the gate start signal is a level turning-on the clock transistor.

11. The display device of claim 9 , wherein the voltage level of the Q node is changed in accordance with a cycle of the gate clock signal in a period that the voltage level of the gate start signal is a level turning-on the clock transistor.

12. The display device of claim 1 , wherein the gate driving circuit further comprising:

a reset transistor electrically connected between a gate node of the pump transistor and an input terminal of a second gate driving voltage, and controlled by the voltage level of the QB node.

13. The display device of claim 12 , wherein a level of the second gate driving voltage is a level turning-off the pump transistor.

14. The display device of claim 1 , wherein the gate driving circuit further comprising:

a boot capacitor electrically connected between the Q node and an output terminal of the gate signal.

15. The display device of claim 14 , wherein a size that the voltage level of the Q node is changed at a timing that the gate signal is changed from a turn-off level to a turn-on level is greater than a size that the voltage level of the Q node is changed in accordance with a change of the gate clock signal.

16. The display device of claim 1 , wherein each of the plurality of subpixels comprising:

a light-emitting element;

a driving transistor supplying a driving current to the light-emitting element; and

a plurality of switching transistors controlling a driving timing of the driving transistor and the light-emitting element,

wherein the gate signal is supplied for controlling the switching transistor having the longest turn-on period in a frame period among the plurality of switching transistors.

17. A gate driving circuit, comprising:

a pull-up transistor controlled by a voltage level of a Q node, and electrically connected between an input terminal of a first gate driving voltage and an output terminal of a gate signal;

a pull-down transistor controlled by a voltage level of a QB node, and electrically connected between an input terminal of a second gate driving voltage and the output terminal of the gate signal;

a pump capacitor electrically connected between the Q node and an input terminal of a gate clock signal;

a pump transistor electrically connected between the pump capacitor and the Q node; and

a feed transistor electrically connected between a gate node of the pump transistor and the input terminal of the first gate driving voltage, and controlled by a voltage level of the gate signal,

wherein in a period that the pump transistor is turned-on, a difference between the voltage level of the Q node and a voltage level of the light-emitting control signal increases, and

wherein the gate signal is the light-emitting control signal.