Method and apparatus for data decoding in communication or broadcasting system
An apparatus and method for efficiently decoding a low-density parity-check (LDPC) code in a communication or broadcasting system are provided. The disclosure relates to performing decoding of an LDPC code by using layered scheduling or a method equivalent thereto, and provides an LDPC decoding apparatus and method for improving decoding performance without increasing decoding complexity by applying appropriate decoding scheduling according to structural or algebraic characteristics of an LDPC code.
1. A decoding method in a wireless communication system, the method comprising:
receiving a signal;
identifying a size of a code block, based on a number of input bits of the signal;
identifying a parity check matrix corresponding to the size of the code block;
identifying a higher priority layer of the parity check matrix based on a degree of a layer within column blocks corresponding to punctured information word bits; and
performing layered decoding based on the parity check matrix corresponding to the size of the code block,
wherein the layered decoding is configured so that the higher priority layer is decoded preferentially over a layer other than the higher priority layer.
2. The method of claim 1 ,
wherein the degree of the layer within column blocks corresponding to punctured information word bits is one of 1 or 0,
wherein the identifying of the higher priority layer of the parity check matrix is further based on a degree of a check node, and
wherein the performing of the layered decoding comprises:
decoding the higher priority layer; and
sequentially decoding layers corresponding to the remaining row blocks.
3. The method of claim 1 , wherein the performing of the layered decoding comprises:
identifying a number of effective row blocks in the parity check matrix;
decoding the higher priority layer; and
decoding layers corresponding to the remaining row blocks in a reverse order, based on the number of the effective row blocks.
4. The method of claim 3 , wherein the number of the effective row blocks is identified based on the number of input bits of the signal, a number of column blocks used for information word transmission, a number of punctured column blocks of the parity check matrix, and the size of the code block.
5. The method of claim 1 , wherein the identifying of the higher priority layer is further based on a code rate for the decoding and a reference code rate.
6. The method of claim 1 ,
wherein the layered decoding is further based on a decoding order predetermined based on a base matrix of the parity check matrix, and
wherein the decoding order is determined based on a transport block size, a number of higher priority layers, and a code rate.
7. The method of claim 6 ,
wherein the decoding order is configured to be:
in case that the parity check matrix is based on a first base graph (base graph #1), [42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43, 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]; or
in case that the parity check matrix is based on a second base graph (base graph #2), [22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15, 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3], and
wherein respective entries refer to numbers of row blocks of the parity check matrix.
8. The method of claim 6 , wherein the layered decoding is further based on the decoding order based on an index of an effective row block from among indexes of row blocks included in the decoding order.
9. The method of claim 6 ,
wherein the decoding order varies depending on a modulation scheme applied to the signal, and
wherein the modulation scheme is one of quadrature phase shift keying (QPSK), 16 quadrature amplitude modulation (QAM), 64 QAM, 256 QAM, and 1024 QAM.
10. A device in a wireless communication system, the device comprising:
a transceiver;
a controller coupled with the transceiver; and
memory storing instructions that, when executed by the controller, cause the device to:
receive a signal,
identify a size of a code block, based on a number of input bits of the signal,
identify a parity check matrix corresponding to the size of the code block,
identify a higher priority layer of the parity check matrix based on a degree of a layer within column blocks corresponding to punctured information word bits, and
perform layered decoding based on the parity check matrix corresponding to the size of the code block,
wherein the layered decoding is configured so that the higher priority layer is decoded preferentially over a layer other than the higher priority layer.
11. The device of claim 10 ,
wherein the degree of the layer within column blocks corresponding to punctured information word bits is one of 1 or 0,
wherein the identifying of the higher priority layer of the parity check matrix is further based on a degree of a check node, and
wherein the memory further comprises the instructions that, when executed by the controller, cause the device to:
decode the higher priority layer, and
sequentially decode layers corresponding to the remaining row blocks.