Reusing remote registers in processing in memory
Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N−1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.
1. An apparatus comprising:
a memory controller comprising circuitry configured to:
access a cache responsive to receipt of an operation targeting a processing device, wherein the operation references a value;
convert the operation into at least two commands that include a memory access command and an arithmetic command, responsive to the value not being in the cache; and
convert the operation into one or more commands that exclude the memory access command and include the arithmetic command, responsive to the value being in the cache.
2. The apparatus as recited in claim 1 , wherein converting the operation into one or more commands that exclude the memory access command causes a reduction in a number of commands that are executed by the processing device.
3. The apparatus as recited in claim 1 , wherein the operation targeting the processing device is a processing in memory command.
4. The apparatus as recited in claim 1 , wherein the one or more commands that exclude the memory access command comprise only the arithmetic command.
5. The apparatus as recited in claim 1 , wherein;
the cache is a constant value cache configured to track values used by requests targeting the processing device; and
the circuitry is configured to store a core identifier and a thread identifier in each of a plurality of entries of the constant value cache.
6. The apparatus as recited in claim 5 , wherein, responsive to an instruction that ends a kernel, the circuitry is configured to reset entries of the plurality of entries storing a core identifier and a thread identifier corresponding to the kernel.
7. The apparatus as recited in claim 1 , wherein the processing device is a processing in memory (PIM) device, and wherein the cache stores the value, responsive to the operation being called by a kernel that invokes a loop with using the value as an invariant variable.
8. A method comprising:
accessing, by circuitry of a control unit of a memory controller, a cache responsive to receipt of an operation targeting a processing device, wherein the operation references a value;
converting, by the control unit of the memory controller, the operation into at least two commands that include at least one memory access command and an arithmetic command, responsive to the value not being in the cache; and
converting the operation into one or more commands that exclude the memory access command and include the arithmetic command, responsive to the value being in the cache.
9. The method as recited in claim 8 , wherein converting the operation into one or more commands that exclude the memory access command causes a reduction in a number of commands that are executed by the processing device.
10. The method as recited in claim 8 , wherein the operation targeting the processing device is a processing in memory command.
11. The method as recited in claim 8 , wherein the one or more commands that exclude the memory access command comprise only the arithmetic command.
12. The method as recited in claim 8 , further comprising:
tracking values used by requests targeting the processing device by the cache that is a constant value cache; and
storing a core identifier and a thread identifier in each of a plurality of entries of the constant value cache.
13. The method as recited in claim 12 , wherein, responsive to an instruction that ends a kernel, the circuitry is configured to reset entries of the plurality of entries storing a core identifier and a thread identifier corresponding to the kernel.
14. The method as recited in claim 8 , wherein the processing device is a processing in memory (PIM) device, and wherein the cache stores the value, responsive to the operation being called by a kernel that invokes a loop using the value as an invariant variable.
15. A system comprising:
a processing in memory (PIM) device; and
a memory controller coupled to the PIM device, wherein the memory controller is comprises circuitry configured to:
access a cache responsive to receipt of a PIM operation targeting the PIM device, wherein the PIM operation references a value;
convert the PIM operation into at least two commands that include a memory access command and an arithmetic command, responsive to the value not being in the cache; and
convert the PIM operation into one or more commands that exclude the memory access command and include the arithmetic command, responsive to the value being in the cache.
16. The system as recited in claim 15 , wherein converting the PIM operation into one or more commands that exclude the memory access command causes a reduction in a number of commands that are executed by the PIM device.
17. The system as recited in claim 15 , wherein the memory controller is configured to prevent a memory access command from being generated for the PIM operation responsive to the value being in the cache.
18. The system as recited in claim 15 , wherein the one or more commands that exclude the memory access command comprise only the arithmetic command.
19. The system as recited in claim 15 , wherein;
the cache is a constant value cache configured to track values used by requests targeting the PIM device; and
the memory controller is configured to store a core identifier and a thread identifier in each of a plurality of entries of the constant value cache.
20. The system as recited in claim 15 19 , wherein, responsive to an instruction that ends a kernel, the circuitry is configured to reset entries of the plurality of entries storing a core identifier and a thread identifier corresponding to the kernel.