Memory devices having vertical transistors and methods for forming the same
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
a first array of memory cells, wherein each of the memory cells comprises a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; and
a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction; and
a first bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the first array of memory cells is coupled to the peripheral circuit across the first bonding interface.
2. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first bonding layer comprising a first bonding contact, and the second semiconductor structure further comprises a second bonding layer comprising a second bonding contact; and
the first bonding contact is in contact with the second bonding contact at the first bonding interface.
3. The 3D memory device of claim 2 , wherein the second semiconductor structure further comprises an interconnect layer comprising the bit lines between the second bonding layer and the first array of memory cells.
4. The 3D memory device of claim 3 , wherein the bit lines are coupled to the peripheral circuit through the interconnect layer, the first bonding layer, and the second bonding layer.
5. The 3D memory device of claim 1 , wherein
the second semiconductor structure further comprises a pad-out interconnect layer; and
the storage units are disposed between the vertical transistors and the pad-out interconnect layer.
6. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a pad-out interconnect layer; and
the peripheral circuit is disposed between the first bonding interface and the pad-out interconnect layer.
7. The 3D memory device of claim 1 , further comprising:
a third semiconductor structure comprising a second array of memory cells, wherein each of the memory cells comprises a vertical transistor extending in the first direction, and a storage unit coupled to the vertical transistor; and
a second bonding interface between the second semiconductor structure and the third semiconductor structure in the first direction, wherein the second array of memory cells is coupled to the peripheral circuit across the first and second bonding interfaces.
8. The 3D memory device of claim 7 , wherein
the storage units in the first array of memory cells are disposed between the second bonding interface and the vertical transistors in the first array of memory cells; and
the storage units in the second array of memory cells are disposed between the second bonding interface and the vertical transistors in the second array of memory cells.
9. The 3D memory device of claim 7 , wherein
the third semiconductor structure further comprises a pad-out interconnect layer; and
the vertical transistors in the second array of memory cells are disposed between the storage units in the second array of memory cells and the pad-out interconnect layer.
10. The 3D memory device of claim 1 , wherein the bit lines are disposed between the vertical transistors and the first bonding interface.
11. The 3D memory device of claim 1 , wherein the vertical transistors are disposed between the storage units and the first bonding interface.
12. The 3D memory device of claim 1 , wherein
the second semiconductor structure further comprises a plurality of word lines each extending in a third direction perpendicular to the first direction and the second direction; and
the vertical transistor comprises:
a semiconductor body extending in the first direction; and
a gate structure in contact with one or more sides of the semiconductor body.
13. The 3D memory device of claim 12 , wherein the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body, respectively, in the first direction.
14. The 3D memory device of claim 13 , wherein
one of the source and the drain of the vertical transistor is coupled to the storage unit in a respective memory cell; and
another one of the source and the drain of the vertical transistor is coupled to the respective bit line.
15. The 3D memory device of claim 12 , wherein two ends of the semiconductor body in the first direction extend beyond the gate structure, respectively.
16. The 3D memory device of claim 12 , wherein one end of the semiconductor body in the first direction is flush with the gate structure.
17. The 3D memory device of claim 12 , wherein:
the gate structure comprises a gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the second direction; and
the gate dielectrics of two adjacent vertical transistors of the vertical transistors in the third direction are continuous.
18. The 3D memory device of claim 12 , wherein:
the gate structure comprises a gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the second direction; and
the gate dielectrics of two adjacent vertical transistors of the vertical transistors in the third direction are separate.
19. The 3D memory device of claim 1 , wherein the memory cells comprise at least a dynamic random-access memory (DRAM) cell, a phase-change memory (PCM) cell, or a ferroelectric RAM (FRAM) cell.
20. A memory system, comprising:
a memory device configured to store data, and comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, wherein each of the memory cells comprises a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; and
a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction; and
a first bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the first bonding interface; and
a memory controller coupled to the memory device and configured to control the array of memory cells through the peripheral circuit and the bit lines.