IP Library › Granted Patent US 12,176,439
Granted Patent B2
US 12,176,439 · App. 17/428,753 · Granted Dec 24, 2024

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Erika Takahashi (Kanagawa, JP); Tsutomu Murakawa (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Katsuaki Tochibayashi (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78696H01L29/045H01L29/66969H01L29/7869
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Quick Facts
Patent No.
US 12,176,439
App. No.
17/428,753
Granted
Dec 24, 2024
Kind
B2
Abstract

A semiconductor device with small fluctuations in transistor characteristics can be provided. The semiconductor device includes a first oxide, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide and between the second oxide and the third oxide, a first insulator over the fourth oxide, and a third conductor over the first insulator. The first oxide includes a groove in a region not overlapping with the second oxide and the third oxide. The first oxide includes a first layered crystal substantially parallel to the surface where the first oxide is formed. In the groove, the fourth oxide includes a second layered crystal substantially parallel to the surface where the first oxide is formed. A concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and in the vicinity of the interface is less than or equal to 5.0 atomic %.

Claims (65)

1. A semiconductor device comprising:

a first oxide;

a second oxide and a third oxide over the first oxide;

a first conductor over the second oxide;

a second conductor over the third oxide;

a fourth oxide over the first oxide and between the second oxide and the third oxide;

a fifth oxide over the fourth oxide,

a first insulator over the fifth oxide; and

a third conductor over the first insulator,

wherein the first oxide comprises a groove in a region not overlapping with the second oxide and the third oxide,

wherein the first oxide comprises a first layered crystal parallel or substantially parallel to a surface where the first oxide is formed,

wherein in the groove, the fourth oxide comprises a second layered crystal parallel or substantially parallel to the surface where the first oxide is formed,

wherein at least one of a concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and a concentration of aluminum atoms in a region adjacent to the interface is less than or equal to 2.0 atomic %, and

wherein a difference between a level at an interface between the first oxide and the second oxide and a level at an interface between the fourth oxide and the fifth oxide is smaller than a thickness of the fourth oxide.

2. A semiconductor device comprising:

a first oxide;

a second oxide and a third oxide over the first oxide;

a first conductor over the second oxide;

a second conductor over the third oxide;

a fourth oxide over the first oxide and between the second oxide and the third oxide;

a fifth oxide over the fourth oxide;

a first insulator over the fifth oxide; and

a third conductor over the first insulator,

wherein the first oxide comprises a groove in a region not overlapping with the second oxide and the third oxide,

wherein the first oxide comprises a first layered crystal parallel or substantially parallel to a surface where the first oxide is formed,

wherein in the groove, the fourth oxide comprises a second layered crystal parallel or substantially parallel to the surface where the first oxide is formed,

wherein on a side wall of the groove, an a-b plane of the first layered crystal and an a-b plane of the second layered crystal are continuously connected, and

wherein at least one of a concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and a concentration of aluminum atoms in a region adjacent to the interface is less than or equal to 2.0 atomic %.

3. The semiconductor device according to claim 1 ,

wherein the first layered crystal and the second layered crystal each comprise a c-axis perpendicular or substantially perpendicular to the surface where the first oxide is formed.

4. The semiconductor device according to claim 1 ,

wherein at least one of the first oxide and the fourth oxide comprise a CAAC structure in the region adjacent to a lower edge portion of the first conductor and in the region adjacent to a lower edge portion of the second conductor.

5. The semiconductor device according to claim 2 ,

wherein a difference between a level at an interface between the first oxide and the second oxide and a level at an interface between the fourth oxide and the fifth oxide is smaller than a thickness of the fourth oxide.

6. The semiconductor device according to claim 2 ,

wherein the first oxide, the fourth oxide, and the fifth oxide each comprise indium, an element M, and zinc,

wherein the element M is at least one of gallium, aluminum, yttrium, and tin,

wherein an atomic ratio of indium to the element M in the first oxide is higher than an atomic ratio of indium to the element M in the fifth oxide, and

wherein an atomic ratio of indium to the element M in the fourth oxide is higher than the atomic ratio of indium to the element M in the fifth oxide.

7. The semiconductor device according to claim 6 ,

wherein the fourth oxide is a metal oxide with a composition of In:Ga:Zn=4:2:3 [atomic ratio] or in a neighborhood of the composition.

8. The semiconductor device according to claim 2 ,

wherein the first layered crystal and the second layered crystal each comprise a c-axis perpendicular or substantially perpendicular to the surface where the first oxide is formed.

9. The semiconductor device according to claim 2 ,

wherein at least one of the first oxide and the fourth oxide comprise a CAAC structure in a region adjacent to a lower edge portion of the first conductor and in a region adjacent to a lower edge portion of the second conductor.

10. A semiconductor device comprising:

a first oxide;

a first conductor and a second conductor over the first oxide;

a second oxide over the first oxide and between the first conductor and the second conductor;

a first insulator over the second oxide; and

a third conductor over the first insulator,

wherein the first oxide comprises a groove in a region not overlapping with the first conductor and the second conductor,

wherein the first oxide comprises a first layered crystal parallel or substantially parallel to a surface where the first oxide is formed,

wherein in the groove, the second oxide comprises a second layered crystal parallel or substantially parallel to the surface where the first oxide is formed,

wherein on a side wall of the groove, an a-b plane of the first layered crystal and an a-b plane of the second layered crystal are continuously connected, and

wherein at least one of a concentration of aluminum atoms at an interface between the first oxide and the second oxide and a concentration of aluminum atoms in a region adjacent to the interface is less than or equal to 2.0 atomic%.

11. The semiconductor device according to claim 10 ,

wherein the first oxide and the second oxide each comprise indium, an element M, and zinc, and

wherein the element M is at least one of gallium, aluminum, yttrium, and tin.

12. The semiconductor device according to claim 11 ,

wherein the second oxide is a metal oxide with a composition of In:Ga:Zn=4:2:3 [atomic ratio] or in a neighborhood of the composition.

13. The semiconductor device according to claim 10 ,

wherein the first layered crystal and the second layered crystal each comprise a c-axis perpendicular or substantially perpendicular to the surface where the first oxide is formed.

14. The semiconductor device according to claim 10 ,

wherein at least one of the first oxide and the second oxide comprise a CAAC structure in a region adjacent to a lower edge portion of the first conductor and in a region adjacent to a lower edge portion of the second conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2021
From: YAMAZAKI, SHUNPEI; TAKAHASHI, ERIKA; MURAKAWA, TSUTOMU; SASAGAWA, SHINYA; TOCHIBAYASHI, KATSUAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 057092/0561 →
Priority Claims (2)
JP 2019-030918 · Feb 22, 2019 · national
JP 2019-042790 · Mar 8, 2019 · national
Continuity (1)
Related Publication 20220077322A1 · Mar 10, 2022