Bit-cell architecture based in-memory compute
A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.
1. An in-memory-compute memory cell, comprising:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell, wherein the first bit-cell comprises a read-word line, and the second bit-cell comprises a read-word line, and, in an in-memory-compute mode of operation, the in-memory-compute cell XORs data stored in the latches with data provided on the read-word lines.
2. The in-memory-compute cell of claim 1 , wherein the first bit-cell and the second bit-cell are foundry bit-cells.
3. The in-memory-compute cell of claim 2 , wherein the first bit-cell and second bit-cell are eight transistor bit-cells.
4. The in-memory-compute cell of claim 1 , wherein the first bit-cell comprises a read-bit line, and the second bit-cell comprises a read-bit line, and, in the in-memory-compute mode of operation, the in-memory-compute cell XORs feature data stored in the latches with weight data provided on the read-word lines.
5. A memory array, comprising:
a plurality of bit-cells of the memory array arranged as a set of rows of bit-cells of the memory array intersecting a plurality of columns of the memory array; and
a plurality of in-memory-compute (IMC) cells of the memory array arranged as a set of rows of IMC cells of the memory array intersecting the plurality of columns of the memory array, wherein each of the IMC cells of the memory array includes:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell, wherein, the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the array, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines.
6. The memory array of claim 5 , wherein the plurality of bit-cells, the first bit-cells of the IMC cells, and the second bit-cells of the IMC cells are foundry bit-cells.
7. The memory array of claim 6 , wherein,
the plurality of bit-cells are six transistor bit-cells; and
the first bit-cells of the IMC cells and the second bit-cells of the IMC cells are eight transistor bit-cells.
8. The memory array of claim 5 , wherein the first bit-cells of the IMC cells comprise a read-bit line, and the second bit-cells of the IMC cells comprise a read-bit line, and, in the in-memory-compute mode of operation of the array, the IMC cells selectively XOR feature data stored in the latches with weight data provided on the read-word lines.
9. The memory array of claim 5 , wherein the array comprises pre-charging circuitry coupled to the plurality of IMC cells.
10. The memory array of claim 9 wherein the pre-charging circuitry comprises masking circuitry, which, in operation, selectively masks outputs of columns of the array.
11. The memory array of claim 5 wherein the set of rows of bit-cells comprises a plurality of rows of bit cells and the set of rows of IMC cells comprises a plurality of rows of IMC cells.
12. The memory array of claim 11 , comprising selection circuitry coupled to the set of rows of IMC cells, wherein the selection circuitry, in operation, selects a row of the plurality of rows of IMC cells.
13. The memory array of claim 11 , wherein the set of rows of IMC cells comprises four rows of IMC cells.
14. The memory array of claim 12 , wherein, in operation, individual rows of the set of rows of IMC cells are configurable to operate in an IMC mode of operation or in a bit-cell mode of operation.
15. A system, comprising:
a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including:
a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and
a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; and
accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the system, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines.
16. The system of claim 15 , wherein the plurality of bit-cells of the plurality of IMC memory arrays, the first bit-cells of the IMC cells, and the second bit-cells of the IMC cells are foundry bit-cells.
17. The system of claim 15 , wherein the first bit-cells of the IMC cells comprise a read-bit line, and the second bit-cells of the IMC cells comprise a read-bit line, and, in the in-memory-compute mode of operation of the system, the IMC cells selectively XOR feature data stored in the latches with weight data provided on the read-word lines.
18. A system, comprising:
a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including:
a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and
a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; and
accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the plurality of IMC memory arrays comprise pre-charging circuitry coupled to the plurality of IMC cells.
19. The system of claim 18 wherein the pre-charging circuitry comprises masking circuitry, which, in operation, selectively masks outputs of columns of the array.
20. The system of claim 15 , wherein the accumulation circuitry comprises a plurality of adders.
21. The system of claim 15 , wherein the accumulation circuitry comprises one or more capacitors.
22. The system of claim 21 , comprising one or more bias capacitors selectively coupleable to the accumulation circuitry.
23. The system of claim 21 , comprising readout circuitry coupled to the one or more capacitors.
24. The system of claim 23 , wherein the readout circuitry comprises an analog-to-digital converter.
25. The system of claim 23 , wherein the readout circuitry comprises a successive approximation circuit.
26. A method, comprising:
storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
storing feature data in one or more rows of the set of rows of IMC cells; and
multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell.
27. The method of claim 26 , comprising controlling an operation mode of individual rows of the set of rows of IMC cells.
28. The method of claim 26 , wherein the multiplying is performed for a set of the plurality of columns and the method comprises accumulating multiplication results for the set of columns.
29. The method of claim 28 , comprising accumulating multiplication results of a plurality of IMC memory arrays.
30. The method of claim 29 , comprising applying a bias to the accumulated multiplication results.
31. The method of claim 29 , comprising generating a classification signal of a neural network based on the accumulated multiplication results of the plurality of IMC memory arrays.
32. A non-transitory computer-readable medium having contents, which, in operation, configure a computing system to perform a method, the method comprising:
storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes:
a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and
a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
storing feature data in one or more rows of the set of rows of IMC cells; and
multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell.
33. The non-transitory computer-readable medium of claim 32 wherein the contents comprise instructions executed by the computing system.