IP Library Granted Patent US 12,183,757
Granted Patent B2
US 12,183,757 · App. 17/619,337 · Granted Dec 31, 2024

Solid-state imaging device

Inventor: Yoshiaki Kitano (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/14634H01L27/14612H01L29/785H04N25/77H04N25/79
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Quick Facts
Patent No.
US 12,183,757
App. No.
17/619,337
Filed
Dec 15, 2021
Granted
Dec 31, 2024
Kind
B2
Art Unit
2898
USPC
257/292
Abstract

There is provided a solid-state imaging device including: a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a second substrate including a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor that includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and a through electrode that is provided in the first substrate and the second substrate, and electrically couples the first substrate and the second substrate to each other and is partially in contact with the gate electrode.

Claims (35)

1. A solid-state imaging device, comprising:

a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, wherein a signal electric charge generated in the photoelectric converter is accumulated in the electric charge accumulation section;

a second substrate including a semiconductor layer and a pixel transistor, wherein the semiconductor layer is stacked on the first substrate, and wherein the pixel transistor includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and

a through electrode that is provided in the first substrate and the second substrate, wherein the through electrode electrically couples the first substrate and the second substrate to each other, and wherein the through electrode is partially in contact with the gate electrode,

wherein the semiconductor layer includes at least one fin, and

wherein the gate electrode is opposed to a plurality of surfaces of the fin.

2. The solid-state imaging device according to claim 1 , wherein the gate electrode is opposed to the semiconductor layer in a plurality of directions.

3. The solid-state imaging device according to claim 1 , wherein the semiconductor layer includes a plurality of the fins, and wherein the semiconductor layer further includes an insulating film provided between adjacent ones of the fins.

4. The solid-state imaging device according to claim 1 , wherein the semiconductor layer includes a plurality of the fins, and wherein the semiconductor layer further includes a connecting section that connects adjacent ones of the fins.

5. The solid-state imaging device according to claim 1 , wherein the second substrate further includes an insulating region that divides the semiconductor layer, and wherein the through electrode penetrates through the insulating region.

6. The solid-state imaging device according to claim 1 , wherein the pixel transistor comprises an amplification transistor.

7. The solid-state imaging device according to claim 1 , wherein the through electrode electrically couples the electric charge accumulation section and the gate electrode of the pixel transistor to each other.

8. A solid-state imaging device, comprising:

a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, wherein a signal electric charge generated in the photoelectric converter is accumulated in the electric charge accumulation section;

a second substrate including a semiconductor layer and a pixel transistor, wherein the semiconductor layer is stacked on the first substrate, and wherein the pixel transistor includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and

a through electrode that is provided in the first substrate and the second substrate, wherein the through electrode electrically couples the first substrate and the second substrate to each other, wherein the through electrode is partially in contact with the gate electrode, and wherein the gate electrode has a front surface opposed to the first substrate, and a side surface that is provided in a direction intersecting with the front surface and is in contact with the through electrode.

9. The solid-state imaging device according to claim 8 , wherein the gate electrode includes a horizontal section and a sidewall section, wherein the horizontal section includes the front surface, wherein the sidewall section includes the side surface and is between the semiconductor layer and the through electrode, and wherein the sidewall section is provided in a thickness direction of the semiconductor layer.

10. The solid-state imaging device according to claim 9 , wherein the gate electrode further includes a vertical section that is coupled to the horizontal section and is embedded in a portion in the thickness direction of the semiconductor layer.

11. The solid-state imaging device according to claim 8 , wherein a portion of the front surface of the gate electrode is also in contact with the through electrode.

12. The solid-state imaging device according to claim 8 , wherein the gate electrode is opposed to the semiconductor layer in a plurality of directions.

13. The solid-state imaging device according to claim 8 , wherein the semiconductor layer includes at least one fin, and wherein the gate electrode is opposed to a plurality of surfaces of the fin.

14. The solid-state imaging device according to claim 13 , wherein the semiconductor layer includes a plurality of the fins, and wherein the semiconductor layer further includes an insulating film provided between adjacent ones of the fins.

15. The solid-state imaging device according to claim 13 , wherein the semiconductor layer includes a plurality of the fins, and wherein the semiconductor layer further includes a connecting section that connects adjacent ones of the fins.

16. A solid-state imaging device, comprising:

a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, wherein a signal electric charge generated in the photoelectric converter is accumulated in the electric charge accumulation section;

a second substrate including a semiconductor layer and a pixel transistor, wherein the semiconductor layer is stacked on the first substrate, and wherein the pixel transistor includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and

a through electrode that is provided in the first substrate and the second substrate, wherein the through electrode electrically couples the first substrate and the second substrate to each other, and wherein the through electrode is partially in contact with the gate electrode, wherein a through hole is provided in the gate electrode, and wherein the through electrode is in contact with an inner peripheral surface of the through hole.

17. The solid-state imaging device according to claim 16 , wherein the gate electrode is opposed to the semiconductor layer in a plurality of directions.

18. The solid-state imaging device according to claim 16 , wherein the semiconductor layer includes at least one fin, and wherein the gate electrode is opposed to a plurality of surfaces of the fin.

19. The solid-state imaging device according to claim 18 , wherein the semiconductor layer includes a plurality of the fins, and wherein the semiconductor layer further includes an insulating film provided between adjacent ones of the fins.

20. A solid-state imaging device, comprising:

a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, wherein a signal electric charge generated in the photoelectric converter is accumulated in the electric charge accumulation section;

a second substrate including a semiconductor layer and a pixel transistor, wherein the semiconductor layer is stacked on the first substrate, wherein the pixel transistor includes a gate electrode opposed to the semiconductor layer, and wherein the pixel transistor reads the signal electric charge of the electric charge accumulation section;

a through electrode that is provided in the first substrate and the second substrate, wherein the through electrode electrically couples the first substrate and the second substrate to each other, and wherein the through electrode is partially in contact with the gate electrode; and

a shared coupling section that is coupled to a plurality of the electric charge accumulation sections and is provided in the first substrate, wherein—an end of the through electrode is in contact with the shared coupling section.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2021
From: KITANO, YOSHIAKI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 058395/0464 →
Priority Claims (1)
JP 2019-118474 · Jun 26, 2019 · national
Continuity (1)
Related Publication 20220367552A1 · Nov 17, 2022
Cited By (1)
US 12,720,902