IP Library › Granted Patent US 12,183,795
Granted Patent B2
US 12,183,795 · App. 17/707,548 · Granted Dec 31, 2024

Notch shape of trench gate bottom corner for better breakdown voltage of power MOSFET and IGBT with good trade off to ron and ox reliability

Inventors: Conghui Liu (Qingdao, CN); Peng Li (Qingdao, CN); Min-Hwa Chi (Qingdao, CN)
Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
H01L29/4236H01L29/401H01L29/7397H01L29/7813H01L29/1608H01L29/2003H01L29/66068H01L29/66348H01L29/66522H01L29/66734
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Quick Facts
Patent No.
US 12,183,795
App. No.
17/707,548
Granted
Dec 31, 2024
Kind
B2
Abstract

The present invention provides a device having a trench gate structure and a method of making the same. The device comprises a substrate, a drift region, a well region, a trench gate, a heavily-doped region, and an electrode positioned on the heavily-doped region. The structure of the device is simple to provide good VDMOS and IGBT breakdown voltages, and meanwhile take on-state resistance and reliability of oxide into account.

Claims (22)

1. A device having a trench gate structure, comprising:

a substrate having a first conductivity type, and the substrate having a first main surface and a second main surface opposite to the first main surface;

a drift region formed on the first main surface of the substrate, the drift region having the first conductivity type, and a carrier content of the drift region being lower than that of the substrate;

a well region formed on the drift region, and the well region having a second conductivity type opposite to the first conductivity type;

a trench gate, the trench gate passing through the well region and reaching the drift region, a bottom corner of two sides of the trench gate having a recess expanding outwardly, and an internal angle of the recess being less than 90°;

a heavily-doped region formed in the well region and at a side edge of the trench gate, and the heavily-doped region having the first conductivity type; and

an electrode positioned on the heavily-doped region, and the electrode contacting with the heavily-doped region and at least partially extending in the well region.

2. The device having a trench gate structure according to claim 1 , wherein the substrate comprises one of silicon, silicon carbide, germanium and gallium nitride.

3. The device having a trench gate structure according to claim 1 , wherein the electrode is of a metal material.

4. The device having a trench gate structure according to claim 1 , wherein the trench gate comprises a trench, a gate dielectric layer positioned at a trench sidewall and a gate material filling the trench, the gate material comprises at least one of polysilicon, metal and metal silicide, and the gate dielectric layer comprises one of silicon dioxide and silicon nitride layer.

5. The device having a trench gate structure according to claim 1 , wherein the second main surface of the substrate is further formed with a drain to form a VDMOS device.

6. The device having a trench gate structure according to claim 1 , wherein the second main surface of the substrate is formed with a collector region of the second conductivity type, and a surface of the collector region is formed with a collector electrode to form an IGBT device.

7. The device having a trench gate structure according to claim 1 , wherein the internal angle of the recess is between 20˜70°.

8. A method of making a device having a trench gate structure, comprising steps of:

providing a substrate, the substrate having a first conductivity type, and the substrate having a first main surface and a second main surface opposite to the first main surface;

forming a drift region on the first main surface of the substrate, the drift region having the first conductivity type, and a carrier content of the drift region being lower than that of the substrate;

forming a well region on the drift region, and the well region having a second conductivity type opposite to the first conductivity type;

forming a trench gate passing through the well region and reaching the drift region, a bottom corner of two sides of the trench gate having a recess expanding outwardly, and an internal angle of the recess being less than 90°;

forming a heavily-doped region in the well region and at a side edge of the trench gate, and the heavily-doped region having the first conductivity type; and

positioning an electrode on the heavily-doped region, and the electrode contacting with the heavily-doped region and at least partially extending in the well region.

9. The method of making a device having a trench gate structure according to claim 8 , wherein a step of performing anisotropic trench etching along a vertical direction until being close to a desirable depth is performed at first, and then a step of performing isotropic etching at a trench bottom is performed, and the isotropic etching is performed vertically and horizontally at the same time to form the recess.

10. The method of making a device having a trench gate structure according to claim 8 , wherein the internal angle of the recess is adjusted through an isotropic etching rate, an etching time and an etching temperature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2022
From: LIU, CONGHUI; LI, PENG; CHI, MIN-HWA
To: SIEN (QINGDAO) INTEGRATED CIRCUITS CO., LTD.
Reel/Frame 059429/0455 →
Priority Claims (1)
CN 202110361602.X · Apr 2, 2021 · national
Continuity (1)
Related Publication 20220320303A1 · Oct 6, 2022