IP Library › Granted Patent US 12,184,242
Granted Patent B2
US 12,184,242 · App. 18/502,940 · Granted Dec 31, 2024

Two-stage LNA with mutual coupling

Inventors: Rong Jiang (San Diego, CA); Khushali Shah (San Diego, CA)
Assignee: pSemi Corporation
H03F3/193H03F1/56H03F2200/222H03F2200/294H03F2200/372H03F2200/451
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Quick Facts
Patent No.
US 12,184,242
App. No.
18/502,940
Granted
Dec 31, 2024
Kind
B2
Abstract

Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L 1 , L 2 . Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L 1 , L 2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.

Claims (38)

1. A low noise amplifier, including:

(a) a first amplifier stage comprising:

(1) at least one input field effect transistor (FET) each having a gate configured to receive an associated radio frequency (RF) input signal, a source configured to be coupled to an associated degeneration inductor, and a drain; and

(2) a second FET having a gate configured to receive a first bias voltage, a source coupled to the drain of the at least one input FET, and a drain coupled to a first output node;

(b) a second amplifier stage comprising:

(1) a third FET having a gate coupled to the first output node, a source configured to be coupled to an associated degeneration inductor, and a drain; and

(2) a fourth FET having a gate configured to receive a second bias voltage, a source coupled to the drain of the third FET, and a drain coupled to a second output node;

(c) an inductor circuit including:

(1) a first inductor coupled to the output of the first output node and configured to be coupled to a first supply voltage; and

(2) a second inductor coupled to the second output node and configured to be coupled to a second supply voltage;

wherein the first inductor and the second inductor are electromagnetically coupled such that a mutual coupling factor K exists between the first inductor and the second inductor of the inductor circuit.

2. The invention of claim 1 , wherein the mutual coupling factor K is equal to or greater than about −0.5 and less than or equal to about +0.5.

3. The invention of claim 1 , wherein the mutual coupling factor K is equal to or greater than about −0.3 and less than or equal to about +0.3.

4. The invention of claim 1 , wherein the absolute value of the mutual coupling factor K is in a range from and including about 0.3 to and including about 0.5.

5. The invention of claim 1 , further including, for each input FET, a matching network coupled to the gate of such input FET and configured to receive the associated RF input signal.

6. The invention of claim 1 , further including a tuning capacitor coupled between the first output node and the gate of the third FET.

7. The invention of claim 1 , further including a selectable-value capacitor coupled in parallel with a corresponding one of the first inductor and/or the second inductor.

8. The invention of claim 1 , further including a selectable-value resistor coupled in parallel with a corresponding one of the first inductor and/or the second inductor.

9. The invention of claim 1 , wherein the FETs are MOSFETs.

10. The invention of claim 1 , wherein the FETs are MOSFETs made by a silicon-on-insulator process.

11. A low noise amplifier, including:

(a) a first amplifier stage comprising:

(1) at least one input field effect transistor (FET) each having a gate configured to receive an associated radio frequency (RF) input signal, a source configured to be coupled to an associated degeneration inductor, and a drain; and

(2) a second FET having a gate configured to receive a first bias voltage, a source coupled to the drain of the at least one input FET, and a drain coupled to a first output node;

(b) a second amplifier stage comprising a third FET having a gate coupled to the first output node, a source configured to be coupled to an associated degeneration inductor, and a drain coupled to a second output node; and

(c) an inductor circuit including:

(1) a first inductor coupled to the output of the first output node and configured to be coupled to a first supply voltage; and

(2) a second inductor coupled to the second output node and configured to be coupled to a second supply voltage;

wherein the first inductor and the second inductor are electromagnetically coupled such that a mutual coupling factor K exists between the first inductor and the second inductor of the inductor circuit.

12. The invention of claim 11 , wherein the mutual coupling factor K is equal to or greater than about −0.5 and less than or equal to about +0.5.

13. The invention of claim 11 , wherein the mutual coupling factor K is equal to or greater than about −0.3 and less than or equal to about +0.3.

14. The invention of claim 11 , wherein the absolute value of the mutual coupling factor K is in a range from and including about 0.3 to and including about 0.5.

15. The invention of claim 11 , further including, for each input FET, a matching network coupled to the gate of such input FET and configured to receive the associated RF input signal.

16. The invention of claim 11 , further including a tuning capacitor coupled between the first output node and the gate of the third FET.

17. The invention of claim 11 , further including a selectable-value capacitor coupled in parallel with a corresponding one of the first inductor and/or the second inductor.

18. The invention of claim 11 , further including a selectable-value resistor coupled in parallel with a corresponding one of the first inductor and/or the second inductor.

19. The invention of claim 11 , wherein the FETs are MOSFETs.

20. The invention of claim 11 , wherein the FETs are MOSFETs made by a silicon-on-insulator process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2024
From: JIANG, RONG; SHAH, KHUSHALI
To: PSEMI CORPORATION
Reel/Frame 066086/0054 →
Continuity (3)
Continuation 17752440 · May 24, 2022
Continuation 16928549 · Jul 14, 2020
Related Publication 20240136984A1 · Apr 25, 2024