IP Library › Granted Patent US 12,185,007
Granted Patent B2
US 12,185,007 · App. 18/091,798 · Granted Dec 31, 2024

Hybrid addressing for imaging and vision data

Inventors: Niraj Nandan (Plano, TX); Mihir Narendra Mody (Bangalore, IN); Rajasekhar Allu (Plano, TX)
Assignee: Texas Instruments Incorporated
H04N25/77
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Quick Facts
Patent No.
US 12,185,007
App. No.
18/091,798
Filed
Dec 30, 2022
Granted
Dec 31, 2024
Kind
B2
Art Unit
2638
USPC
348/207.99
Abstract

In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.

Claims (50)

1. A method, comprising:

receiving image data of an input image having lines therein;

determining a start line for circular addressing of a first portion of the image data;

determining an end line for circular addressing of the first portion of the image data;

determining a start line and an end line for a second portion of the image data, wherein the second portion is non-overlapping with the first portion;

storing the second portion of the image data in a linear buffer in a first memory;

storing the first portion of the image data in a circular buffer in a second memory;

processing the second portion of the image data to produce a first block of an output image; and

processing the first portion of the image data to produce a second block of the output image.

2. The method of claim 1 , wherein the linear buffer is a first linear buffer, and the method further comprises:

determining a start line and an end line for a third portion of the image data, wherein the third portion is non-overlapping with the first portion and the second portion;

storing the third portion of the image data in a second linear buffer in the second memory; and

processing the third portion of the image data to produce a third block of the output image.

3. The method of claim 1 , wherein the circular buffer is stored in on-chip memory.

4. The method of claim 1 , wherein the linear buffer is stored in off-chip memory.

5. The method of claim 1 , further comprising retrieving the second portion of the image data from a top of the input image, and processing the second portion of the image data before processing the first portion of the image data.

6. The method of claim 1 , wherein the first portion of the image data includes a center line of the input image.

7. The method of claim 1 , wherein the second portion of the image data includes a line at an edge of the input image.

8. The method of claim 1 , further comprising selecting the start line for circular addressing and the end line for circular addressing based at least in part on a size of the circular buffer.

9. A method, comprising:

receiving image data of an input image having lines therein;

storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image;

storing a second portion of the image data in a linear buffer in a second memory, wherein the second portion is non-overlapping with the first portion;

processing the second portion of the image data to produce a first block of an output image; and

processing the first portion of the image data to produce a second block of the output image.

10. The method of claim 9 , wherein the linear buffer is a first linear buffer, and the method further comprises:

storing a third portion of the image data in a second linear buffer in the second memory, wherein the third portion is non-overlapping with the first portion and the second portion; and

processing the third portion of the image data to produce a third block of the output image.

11. The method of claim 9 , wherein the circular buffer is stored in on-chip memory.

12. The method of claim 9 , wherein the linear buffer is stored in off-chip memory.

13. The method of claim 9 , further comprising retrieving the second portion of the image data from a top portion of the input image, and processing the second portion of the image data before processing the first portion of the image data.

14. The method of claim 9 , further comprising retrieving the second portion of the image data from a top portion of the input image, and storing the second portion of the image data before storing the first portion of the image data.

15. The method of claim 9 , further comprising retrieving the second portion of the image data from a bottom portion of the input image, and processing the second portion of the image data after processing the first portion of the image data.

16. The method of claim 9 , further comprising retrieving the second portion of the image data from a bottom portion of the input image, and storing the second portion of the image data after storing the first portion of the image data.

17. A system, comprising:

a vision imaging subsystem configured to receive image data of an input image having lines therein;

processing circuitry configured to:

determine a start line for circular addressing of a first portion of the image data;

determine an end line for circular addressing of the first portion of the image data;

determine a start line and an end line for a second portion of the image data, wherein the second portion is non-overlapping with the first portion;

a first memory configured to store the second portion of the image data in a linear buffer;

a second memory configured to store the first portion of the image data in a circular buffer;

wherein the processing circuitry is further configured to process the second portion of the image data to produce a first block of an output image; and

wherein the processing circuitry is further configured to process the first portion of the image data to produce a second block of the output image.

18. The system of claim 17 , wherein the linear buffer is a first linear buffer, and the processing circuitry is further configured to:

determine a start line and an end line for a third portion of the image data, wherein the third portion is non-overlapping with the first portion and the second portion;

store the third portion of the image data in a second linear buffer in the second memory; and

process the third portion of the image data to produce a third block of the output image.

19. The system of claim 17 , wherein the processing circuitry is configured to select the start line for circular addressing and the end line for circular addressing based at least in part on a size of the circular buffer.

20. The system of claim 17 , wherein the circular buffer is stored in on-chip memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2023
From: NANDAN, NIRAJ; MODY, MIHIR NARENDRA; ALLU, RAJASEKHAR
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 062328/0158 →
Continuity (2)
Provisional Application 63391400 · Jul 22, 2022
Related Publication 20240031704A1 · Jan 25, 2024
Cited By (1)
US 12,720,232