Array substrate and manufacturing method thereof
The present invention provides an array substrate and a manufacturing method thereof, the array substrate forms a dual U-shaped conductor structure encompassing a first thin film transistor and a second thin film transistor by a first light shielding layer, a second light shielding layer, a first shielding layer, and a second shielding layer to perfectly shield moving charges in the film layer under the thin film transistor and the film layers on two sides of the thin film transistor outside the dual U-shaped conductor structure to keep excellent electrical properties of a device.
1. An array substrate, comprising:
a first thin film transistor and a second thin film transistor disposed on a base layer;
a first light shielding layer disposed under the first thin film transistor and disposed opposite to a first active layer in the first thin film transistor;
a second light shielding layer disposed under the second thin film transistor and disposed opposite to a second active layer of the second thin film transistor, wherein a bottom surface of the second light shielding layer is connected to the first light shielding layer;
a first shielding layer disposed on a side of the first thin film transistor away from the second thin film transistor, wherein an end of the first shielding layer is electrically connected to a first source and drain electrode of the first thin film transistor, and another end of the first shielding layer is electrically connected to the first light shielding layer; and
a second shielding layer disposed on a side of the second thin film transistor away from the first thin film transistor, wherein an end of the second shielding layer is electrically connected to a second source and drain electrode of the second thin film transistor, and another end of the second shielding layer is electrically connected to the second light shielding layer;
wherein the first active layer and the second active layer are located between the first shielding layer and the second shielding layer;
wherein a buffer layer is disposed between the base layer and the first thin film transistor, or disposed between the base layer and the second thin film transistor;
wherein the first thin film transistor comprises: a first insulation layer disposed on the buffer layer, wherein the first active layer is disposed in the first insulation layer; a first gate electrode disposed on a surface of the first insulation layer away from the buffer layer and disposed opposite to the first active layer; a first dielectric layer disposed on the first insulation layer and covering the first gate electrode; and
a first source and drain electrode disposed on a surface of the first dielectric layer away from the first gate electrode;
wherein the first source and drain electrode comprises: a first drain electrode, wherein a bottom surface of first drain electrode comprises a first protrusion portion, the first protrusion portion extends through the first dielectric layer and the first insulation layer and is electrically connected to the first active layer; and a first source electrode, wherein a bottom surface of first source electrode comprises a second protrusion portion, the second protrusion portion extends through the first dielectric layer and the first insulation layer and is electrically connected to the first active layer;
wherein the first active layer is entirely encircled in the first insulation layer, the buffer layer comprises a first recess, and a recess opening of the first recess faces the first active layer, the first light shielding layer is disposed on a bottom surface of the first recess, and the first insulation layer is disposed on the buffer layer and is filled in the first recess.
2. The array substrate according to claim 1 , wherein
the second thin film transistor comprises:
a second dielectric layer disposed between the first dielectric layer and the first source and drain electrode;
the second active layer disposed between the first dielectric layer and the second dielectric layer, or disposed in the second dielectric layer;
a second insulation layer disposed on a surface of the second active layer away from the first dielectric layer;
a second gate electrode disposed on a surface of the second insulation layer away from the second active layer; and
the second source and drain electrode disposed on a surface of the second dielectric layer away from the second gate electrode; and
the second source and drain electrode comprises:
a second drain electrode, wherein a bottom surface of second drain electrode comprises a third protrusion portion, the third protrusion portion extends through the second dielectric layer and is electrically connected to the second active layer, and an end of the second drain electrode near the first thin film transistor is electrically connected to the first source electrode; and
a second source electrode, wherein a bottom surface of second source electrode comprises a fourth protrusion portion, the fourth protrusion portion extends through the second dielectric layer and is electrically connected to the second active layer.
3. The array substrate according to claim 2 , wherein when the second active layer is disposed in the second dielectric layer, the first dielectric layer comprises a second recess, and a recess opening of the second recess faces the second active layer;
the second light shielding layer is disposed on a bottom surface of the second recess; and
the second dielectric layer is disposed on the first dielectric layer and is filled in the second recess.
4. The array substrate according to claim 2 , further comprising:
a third shielding layer located between the second protrusion portion and the third protrusion portion;
wherein an end of the third shielding layer is electrically connected to the second light shielding layer, and another end of the third shielding layer extends through the second dielectric layer and is electrically connected to the first source electrode and the second drain electrode.