DC voltage regulator for low-power device
This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.
1. An apparatus comprising:
a supply voltage regulator circuit configured to regulate a power supply voltage of a main circuit;
a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal;
a clock signal generator circuit configured to generate the clock signal; and
a dummy circuit configured to emulate the main circuit and to follow operational behavior of the circuit and, thereby, cause the clock signal generator circuit to change a frequency in response to a change in operational conditions of the main circuit,
wherein the clock signal generator circuit is configured to output the clock signal and, thereby, switch the comparator circuit on and off only in a power-save mode of the main circuit, and wherein the comparator circuit is continuously on in an active mode of the main circuit.
2. The apparatus of claim 1 , wherein the dummy circuit is configured such that power leakage in the dummy circuit correlates with power leakage in the main circuit.
3. The apparatus of claim 1 , wherein the operational conditions comprise temperature-dependent behavior of the main circuit.
4. The apparatus of claim 1 , further comprising a reference voltage generator circuit, coupled to receive the clock signal as an input, and configured when enabled by the clock signal to generate a reference current defining the reference voltage and, further, to generate an enablement signal enabling the comparator circuit to sample the power supply voltage.
5. The apparatus of claim 4 , wherein the reference voltage generator circuit is configured to generate the enablement signal after the reference current has settled.
6. The apparatus of claim 4 , wherein the enablement signal is a clock signal.
7. The apparatus of claim 1 , wherein the clock signal generator circuit is operated by a nanoampere level bias current.
8. The apparatus of claim 1 , wherein if the sampled power supply voltage is above the reference voltage, the comparator circuit is configured not to enable the supply voltage regulator circuit to charge the power supply voltage.
9. The apparatus of claim 1 , wherein a periodicity of the clock signal is between 0.1 and 100 milliseconds.
10. An apparatus comprising:
a supply voltage regulator circuit configured to regulate a power supply voltage of a main circuit;
a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal;
a clock signal generator circuit configured to generate the clock signal; and
a dummy circuit configured to emulate the main circuit and to follow operational behavior of the main circuit such that power leakage in the dummy circuit correlates with power leakage in the main circuit and, thereby, cause the clock signal generator circuit to change the frequency in response to a change in the operational conditions,
wherein the clock signal generator circuit is configured to output the clock signal and, thereby, switch the comparator circuit on and off only in a power-save mode of the main circuit, and wherein the comparator circuit is continuously on in an active mode of the main circuit.