Error checking for systolic array computation
Aspects of the disclosure are directed to a computation unit implementing a systolic array and configured for detecting errors while processing data on the systolic array. Checksum circuit in communication with a systolic array is configured to compute checksums and perform error detection while the systolic array processes input data. Instead of pre-generating checksums in input matrices, input matrices can be directly fed into the systolic array through the checksum circuit. On the output side, the checksum circuit can generate and compare checksums with checksums in an output matrix generated by the systolic array. Error checking the operations to generate the output matrix can be performed without delaying the operations of the systolic array, and without preprocessing the input matrices.
1. A computation unit comprising:
one or more processing elements configured to:
receive first input elements from a first input matrix and second input elements from a second input matrix; and
generate an output matrix from the first input elements and the second input elements; and
an output checksum circuit configured to receive the output matrix, and determine, from the output matrix, an occurrence of one or more errors in the generation of the output matrix.
2. The computation unit of claim 1 , wherein, to determine the occurrence of one or more errors in the generation of the output matrix, the output checksum circuit is further configured to:
generate, from at least one row of the output matrix, a row checksum;
compare the row checksum with a checksum in an output checksum column; and
determine, from the comparison, whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold.
3. The computation unit of claim 2 , wherein, to determine whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold, the output checksum circuit is further configured to determine whether an absolute difference between the row checksum and the checksum in the output checksum column are within a predetermined threshold.
4. The computation unit of claim 1 , wherein to determine the occurrence of one or more errors in the generation of the output matrix, the output checksum circuit is further configured to:
generate, from at least one column of the output matrix, a column checksum;
compare the column checksum with a checksum in an output checksum row; and
determine, from the comparison, whether the column checksum matches with the checksum in the output checksum row within a predetermined threshold.
5. The computation unit of claim 1 , wherein, in response to the determination of the occurrence of one or more errors in the generation of the output matrix, the output checksum circuit is further configured to send an indication of the occurrence of one or more errors to one or more devices.
6. The computation unit of claim 5 , wherein the one or more processing elements are further configured to, in response to sending the indication of the occurrence of one or more errors to the one or more devices, receive an adjusted voltage higher than a critical voltage for the computation unit.
7. The computation unit of claim 6 , wherein the one or more processing elements are further configured to receive a first voltage lower than the critical voltage for the computation unit until receiving the adjusted voltage.
8. The computation unit of claim 1 , wherein the first input elements and the second input elements are floating point values.
9. A method for data processing by a computation unit, the method comprising:
receiving, by one or more processing elements, first input elements from a first input matrix;
receiving, by the one or more processing elements, second input elements from a second input matrix;
generating, by the one or more processing elements, an output matrix from the first input elements and the second input elements;
receiving, by an output checksum circuit, the output matrix; and
determining, by the output checksum circuit, from the output matrix, an occurrence of one or more errors in the generation of the output matrix.
10. The method of claim 9 , wherein determining the occurrence of one or more errors in the generation of the output matrix further comprises:
generating, from at least one row of the output matrix, a row checksum;
comparing the row checksum with a checksum in an output checksum column; and
determining, from the comparison, whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold.
11. The method of claim 10 , wherein determining whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold further comprises determining whether an absolute difference between the row checksum and the checksum in the output checksum column are within a predetermined threshold.
12. The method of claim 9 , wherein determining the occurrence of one or more errors in the generation of the output matrix further comprises:
generating, from at least one column of the output matrix, a column checksum;
comparing the column checksum with a checksum in an output checksum row; and
determining, from the comparison, whether the column checksum matches with the checksum in the output checksum row within a predetermined threshold.
13. The method of claim 9 , further comprising sending, by the output checksum circuit, an indication of the occurrence of one or more errors to one or more devices.
14. The method of claim 13 , further comprising receiving, by the one or more processing elements, an adjusted voltage higher than a critical voltage for the computation unit.
15. The method of claim 14 , further comprising receiving, by the one or more processing elements, a first voltage lower than the critical voltage for the computation unit until receiving the adjusted voltage.
16. The method of claim 9 , wherein the first input elements and the second input elements are floating point values.
17. A non-transitory computer readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors to performing operations for data processing by a computation unit, the operations comprising:
receiving, by one or more processing elements, first input elements from a first input matrix;
receiving, by the one or more processing elements, second input elements from a second input matrix;
generating, by the one or more processing elements, an output matrix from the first input elements and the second input elements;
receiving, by an output checksum circuit, the output matrix; and
determining, by the output checksum circuit, from the output matrix, an occurrence of one or more errors in the generation of the output matrix.
18. The non-transitory computer readable medium of claim 17 , wherein determining the occurrence of one or more errors in the generation of the output matrix further comprises:
generating, from at least one row of the output matrix, a row checksum;
comparing the row checksum with a checksum in an output checksum column; and
determining, from the comparison, whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold.
19. The non-transitory computer readable medium of claim 18 , wherein determining whether the row checksum matches with the checksum in the output checksum column within a predetermined threshold further comprises determining whether an absolute difference between the row checksum and the checksum in the output checksum column are within a predetermined threshold.
20. The non-transitory computer readable medium of claim 17 , wherein determining the occurrence of one or more errors in the generation of the output matrix further comprises:
generating, from at least one column of the output matrix, a column checksum;
comparing the column checksum with a checksum in an output checksum row; and
determining, from the comparison, whether the column checksum matches with the checksum in the output checksum row within a predetermined threshold.