Multi-format graphics processing unit docking board
A multi-format graphics process unit (GPU) docking board is disclosed. The multi-format GPU docking board includes a first switch to enable communication between a first format (GPU) board and a second format GPU board, and a second switch to enable communication between a central processing unit (CPU) and the first format GPU board and between the CPU and the second format GPU board.
1. A multi-format docking board comprising:
a first switch to enable communication between a first format graphics processing unit (GPU) board with a second format GPU board;
a second switch to enable communication between a central processing unit (CPU) and the first format GPU board, and between the CPU and the second format GPU board;
a ribbon cable between a first bridge connector of the first format GPU board and a second bridge connector of the first switch; and
a board line between a first inlay connector of the first switch and a second inlay connector of the second format GPU board.
2. The multi-format docking board of claim 1 , wherein the first bridge connector and the second bridge connector couple between the first format GPU board and the first switch; and
the first inlay connector and the second inlay connector couple between the first switch and the second format GPU board.
3. The multi-format docking board of claim 1 ,
wherein the first inlay connector couples between the first format GPU board and the second switch;
the second inlay connector couples between the second format GPU board and the second switch; and
a third inlay connector couples between the second switch and the CPU.
4. The multi-format docking board of claim 1 further comprising:
one or more clock circuits for providing a first clock frequency for the first format GPU board and a second clock frequency for the second format GPU board.
5. The multi-format docking board of claim 1 further comprising:
a first communication channel operating at a first bandwidth for first communications between the first format GPU board and the first switch; and
a second communication channel operating at a second bandwidth for second communications between the second format GPU board and the first switch.
6. The multi-format docking board of claim 5 further comprising:
a common communication channel operating at a common clock frequency for the first communications and the second communications.
7. The multi-format docking board of claim 1 further comprising:
at least one processor associated with the first switch; and
memory having instructions for execution on the at least one processor to cause the at least one processor to allocate at least communication resources for the first format GPU board and the second format GPU board.
8. The multi-format docking board of claim 1 , wherein the first bridge connector between the first format GPU board and the first switch provides at least a clock signal referenced from the second format GPU board.
9. The multi-format docking board of claim 1 further comprising:
a peripheral component interconnect express (PCIE®) connector between the first format GPU board and the multi-format docking board; and
an NVLINK™ formatted bridge connector between the first format GPU board and the first switch.
10. The multi-format docking board of claim 1 further comprising:
an SXM™ connector supporting NVLINK™ interconnection standards between the second format GPU board and the multi-format docking board and supporting PCIE® communication standards between the second format GPU board and the multi-format docking board.
11. The multi-format docking board of claim 1 further comprising:
an NVLINK™ interconnection standards switch forming the first switch; and a PCIE® switch forming the second switch.
12. A switch for a docking board comprising:
an inlay connector to enable a first communication between a first format graphics processing unit (GPU) board on the docking board and a central processing unit (CPU) and to enable a second communication between a second format GPU board on the docking board and the CPU, wherein the inlay connector is connected by a board line to another inlay connector of another switch and enables a third communication between the first format GPU board and the second format GPU board; and
a bridge connector that connects via a ribbon cable to another bridge connector of the first format GPU board.
13. The switch of claim 12 further comprising:
a clock receiver circuit to receive clock signals from a clock generator of the docking board.
14. The switch of claim 12 further comprising:
at least one processor; and
memory having instructions for execution on the at least one processor to cause the at least one processor to receive identifiers for the first format GPU board and for the second format GPU board, to allocate resources for the first format GPU board and for the second format GPU board, and to communicate the identifiers to the CPU.
15. The switch of claim 12 further comprising:
the inlay connector adapted to couple with a second inlay connector of the docking board, to enable communication between the first format GPU board and the CPU, and between the second format GPU and the CPU, through board lines within the docking board.
16. The switch of claim 12 further comprising:
a peripheral component interconnect express (PCIE®) connector forming the inlay connector.
17. The switch of claim 12 further comprising: at least one processor; and
memory having instructions for execution on the at least one processor to cause the at least one processor to communicate with an operating system associated with the CPU through at least a GPU driver associated with the CPU.
18. A switch for enabling a multi-format docking board, the switch comprising:
a bridge connector to enable communication, via a ribbon cable, between a first format graphics processing unit (GPU) board and the switch;
one or more inlay connectors to enable communication between a central processing unit (CPU) and a second format GPU board and to enable communication between the CPU and the first format GPU board, wherein at least one of the one or more in lay connectors is connected to the first or the second format GPU board through a board line; and
NVLINK™ interconnection standards for the bridge connector for supporting communications between the first format GPU board, the switch, and the second format GPU board.
19. The switch of claim 18 further comprising:
at least one processor; and
memory having instructions for execution on the at least one processor to cause the at least one processor to allocate at least communication resources for the first format GPU board and the second format GPU board to communicate with each other using NVLINK™ interconnection standards.
20. A method for operating a multi-format docking board, comprising: enabling a first switch for communication between a first format graphics processing unit (GPU) board and a second format GPU board;
enabling a second switch for communication between a central processing unit (CPU) and the first format GPU board, and between the CPU and the second format GPU board;
enabling a ribbon cable between a first bridge connector of the first format GPU board and a second bridge connector of the first switch; and
enabling a board line between a first inlay connector of the first switch and a second inlay connector of the second format GPU board.
21. The method of claim 20 further comprising:
coupling, using at least the first bridge connector, the first format GPU board to the first switch; and
coupling, using at least the first inlay connector, the first switch to the second format GPU board.
22. The method of claim 20 further comprising:
providing the first inlay connector for coupling between the first format GPU board and the second switch;
providing the second inlay connector for coupling between the second format GPU board and the second switch; and
providing a third inlay connector for coupling between the second switch and the CPU.
23. The method of claim 20 further comprising:
providing, using one or more clock circuits, a first clock frequency for the first format GPU board and a second clock frequency for the second format GPU board.
24. The method of claim 20 further comprising:
enabling a first communication channel operating at a first bandwidth for first communications between the first format GPU board and the first switch; and
enabling a second communication channel operating at a second bandwidth for second communications between the second format GPU board and the first switch.
25. The method of claim 24 further comprising:
enabling a common communication channel operating at a common clock frequency for the first communications and the second communications.
26. The method of claim 20 further comprising:
allocating, by at least a processor associated with the first switch, at least communication resources for the first format GPU board and the second format GPU board.
27. The method of claim 20 further comprising:
providing, using the first bridge connector between the first format GPU board and the first switch, at least a clock signal referenced from the second format GPU board.