Enhanced techniques for traversing ray tracing acceleration structures
Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.
1. A ray tracing acceleration hardware device, comprising:
memory configured to store at least portions of an acceleration data structure comprising a compressed treelet including a node, one or more child nodes of the node, and a state indicator associated with the node;
ray storage configured to store an operation indicator from a ray received from a processor;
traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified by the operation indicator if the state indicator is in a first state, and (b) ignoring the operation if the state indicator is in a second state; and
intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.
2. The ray tracing acceleration hardware device according to claim 1 , wherein the traversal circuitry is further configured to, if the state indicator is in the second state, traversing a child node of the node without performing the operation on the child node.
3. The ray tracing acceleration hardware device according to claim 1 , wherein the traversal circuitry is further configured to, if the state indicator is in the first state, determine, based on the performed operation whether to traverse a child node of the node, and responsive to a result of the determining either traversing the child node or not traversing the child node.
4. The ray tracing acceleration hardware device according to claim 1 , wherein a data structure of the node includes the state indicator, and wherein the traversal circuitry is further configured to, if the state indicator is in the first state, perform the operation using the operation indicator, and at least one parameter specified in the ray other than the operation indicator and/or at least one parameter specified in a child node of the node.
5. The ray tracing acceleration hardware device according to claim 1 , wherein a data structure of the node includes the state indicator, and wherein the state indicator is a bit.
6. The ray tracing acceleration hardware device according to claim 1 , wherein a data structure of the node includes the state indicator, wherein the state indicator encodes a default action, and wherein the traversal circuitry is further configured to, when the state indicator is in the second state, perform the default action, instead of performing the operation, at the node.
7. The ray tracing acceleration hardware device according to claim 1 , wherein the node is a root node in the compressed treelet and the node includes a node parameter that is used in the logical operation with one or more parameters from the ray.
8. The ray tracing acceleration hardware device according to claim 1 , wherein, whereas the detecting of the one or more intersections is based on x, y and z coordinates associated with the node of the acceleration structure and the ray, the operation is based on parameters other than the x, y and z coordinates associated with the node and the x, y and z coordinates of the ray.
9. The ray tracing acceleration hardware device according to claim 8 , wherein the operation is based on, in addition to the operation indicator, a parameter in the node and parameters in the ray.
10. The ray tracing acceleration hardware device according to claim 9 , wherein the parameters in the ray include a length of the ray.
11. The ray tracing acceleration hardware device according to claim 1 , wherein the compressed treelet is a bottom level acceleration structure (BLAS) compressed treelet, and wherein the traversal circuitry is further configured to, if the state indicator is not set, to perform the logical operation according to the operation indicator at each child node of the node.
12. The ray tracing acceleration hardware device according to claim 11 , wherein the traversal circuitry is further configured to, if the state indicator is set, not performing the operation specified by the operation indicator at any child node of the node.
13. The ray tracing acceleration hardware device according to claim 1 , wherein the state indicator is set in the node, and wherein the traversal circuitry is further configured to, if the state indicator is in the second state, determining, based on an invert bit in a child node of the node, whether or not to traverse the child node without performing the operation on the child node.
14. The ray tracing acceleration hardware device according to claim 1 , wherein the traversal circuitry and the intersection detection circuitry are parts of a server or a data center employed in generating an image, and the image is streamed to a user device.
15. The ray tracing acceleration hardware device according to claim 1 , wherein the traversal circuitry and the intersection detection circuitry are employed in generating an image, and the image is used for training, testing, or certifying a neural network employed in a machine, robot, or autonomous vehicle.
16. A system comprising:
a processor configured to generate a ray including an operation indicator; and
a coprocessor connected to the processor and comprising:
memory configured to store at least portions of an acceleration data structure comprising a compressed treelet including a node, one or more child nodes of the node, and a state indicator associated with the node;
ray storage configured to store the operation indicator from the ray;
traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified in the operation indicator if the state indicator is in a first state, and (b) ignoring the operation if the state indicator is in a second state; and
intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.
17. A method, comprising:
storing in a memory of a hardware coprocessor at least portions of an acceleration data structure comprising a compressed treelet including a node, one or more child nodes of the node, and a state indicator associated with the node;
receiving, in the hardware coprocessor, a ray from a processor, the ray specifying an operation indicator;
storing the operation indicator in a ray storage in the hardware coprocessor;
traversing, by traversal circuitry in the hardware coprocessor, the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified in the operation indicator if the state indicator is in a first state, and (b) ignoring the logical operation if the state indicator is in a second state; and
detecting, by intersection detection circuitry in the hardware coprocessor, one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.