Array substrate and display apparatus
An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤k≤(K/2), and a plurality of fourth reset signal lines in (2k)-th columns of the K columns. A respective third reset signal line and a respective fourth reset signal line have different line patterns.
1. An array substrate, comprising:
K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate;
wherein the K number of reset signal lines comprises:
a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤ k≤ (K/2); and
a plurality of fourth reset signal lines in (2k)-th columns of the K columns;
wherein the array substrate comprises a first interconnected reset signal supply network and a second interconnected reset signal supply network;
wherein the first interconnected reset signal supply network comprises the plurality of third reset signal lines in the (2k−1)-th columns, and a plurality of first reset signal lines respectively cross over the plurality of third reset signal lines; and
the second interconnected reset signal supply network comprises the plurality of fourth reset signal lines in the (2k)-th columns, and a plurality of second reset signal lines respectively cross over the plurality of fourth reset signal lines;
wherein the array substrate further comprises a first initialization connecting line present in a (2k)-th column, and absent in a (2k−1)-th column and a second initialization connecting line present in the (2k−1)-th column, and absent in the (2k)-th column;
wherein the first initialization connecting line in the (2k)-th column connects a respective first reset signal line of the plurality of first reset signal lines and a source electrode of a first reset transistor in a respective pixel driving circuit in the (2k)-th column together;
the second initialization connecting line in the (2k−1)-th column connects a respective second reset signal line of the plurality of second reset signal lines and a source electrode of a second reset transistor in a respective pixel driving circuit in the (2k−1)-th column together;
a respective third reset signal line in the (2k−1)-th column connects a respective first reset signal line of the plurality of first reset signal lines and a source electrode of a first reset transistor in the respective pixel driving circuit in the (2k−1)-th column together; and
a respective fourth reset signal line in the (2k)-th column connects a respective second reset signal line of the plurality of second reset signal lines and a source electrode of a second reset transistor in the respective pixel driving circuit in the (2k)-th column together.
2. The array substrate of claim 1 , wherein a respective first reset signal line is connected to one or more of the plurality of third reset signal lines;
a respective third reset signal line is connected to one or more of the plurality of first reset signal lines;
a respective second reset signal line is connected to one or more of the plurality of fourth reset signal lines; and
a respective fourth reset signal line is connected to one or more of the plurality of second reset signal lines.
3. The array substrate of claim 1 , wherein the plurality of first reset signal lines and the plurality of second reset signal lines extend along a first direction, respectively;
the plurality of third reset signal lines and the plurality of fourth reset signal lines extend along a second direction, respectively; and
the plurality of first reset signal lines and the plurality of second reset signal lines are alternately arranged along the second direction.
4. The array substrate of claim 1 , wherein the plurality of third reset signal lines are substantially parallel to each other;
the plurality of fourth reset signal lines are substantially parallel to each other; and
a respective third reset signal line is non-parallel to a respective fourth reset signal line.
5. The array substrate of claim 1 , wherein a segment of a respective third reset signal line between two adjacent first reset signal lines and a segment of a respective fourth reset signal line between the two adjacent first reset signal lines are non-parallel to each other; or
a segment of a respective third reset signal line between two adjacent second reset signal lines and a segment of a respective fourth reset signal line between the two adjacent second reset signal lines are non-parallel to each other.
6. The array substrate of claim 1 , wherein a respective third reset signal line comprises a first colinear segment, a second colinear segment, and a first non-colinear segment connecting the first colinear segment to the second colinear segment; and
a respective fourth reset signal line comprises a third colinear segment, a fourth colinear segment, and a second non-colinear segment connecting the third colinear segment to the fourth colinear segment.
7. The array substrate of claim 6 , wherein a first distance between connecting points of the first non-colinear segment with the first colinear segment and the second colinear segment is different from a second distance between connecting points of the second non-colinear segment with the third colinear segment and the fourth colinear segment.
8. The array substrate of claim 6 , to wherein the first non-colinear segment deviates from a virtual line connecting the first colinear segment and the second colinear segment by a first maximum distance;
the second non-colinear segment deviates from a virtual line connecting the third colinear segment and the fourth colinear segment by a second maximum distance; and
the first maximum distance is different from the second maximum distance.
9. The array substrate of claim 8 , wherein the first non-colinear segment deviates from the virtual line connecting the first colinear segment and the second colinear segment, and the second non-colinear segment deviates from the virtual line connecting the third colinear segment and the fourth colinear segment, toward a same side of the array substrate.
10. The array substrate of claim 1 , wherein at least in one respective column of pixel driving circuit of the K columns of pixel driving circuits, a total number of pixel driving circuits is P;
in the respective column, a ratio of a total number of reset signal lines extending along a second direction and through P number of pixel driving circuits to a total number of initialization connecting lines is 1:P.
11. The array substrate of claim 1 , further comprising:
a plurality of second voltage supply lines on a side of the plurality of third reset signal lines away from a base substrate; and
a plurality of anodes on a side of the plurality of second voltage supply lines away from the base substrate;
wherein an orthographic projection of at least one anode on the base substrate overlaps with an orthographic projection of a respective second voltage supply line on the base substrate and an orthographic projection of a respective third reset signal line on the base substrate.
12. A display apparatus, comprising the array substrate of claim 1 , and an integrated circuit connected to the array substrate.
13. An array substrate, comprising:
K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate;
wherein the K number of reset signal lines comprises:
a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤k≤(K/2); and
a plurality of fourth reset signal lines in (2k)-th columns of the K columns;
wherein the array substrate comprises a semiconductor material layer;
wherein, in a respective subpixel, the semiconductor material layer comprises an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion that is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel; and
at least 50% of an orthographic projection of the third node portion on a base substrate is non-overlapping with an orthographic projection of a respective third reset signal line or a respective fourth reset signal line on the base substrate.
14. The array substrate of claim 13 , wherein the third node portion comprises a first part connecting the active layer of the third transistor to the active layer of the fifth transistor, the first part extending along a second direction; and a second part connecting the first part to the active layer of the driving transistor, the second part extending along a first direction.
15. The array substrate of claim 14 , wherein, in a (2k−1)-th column, a first non-colinear segment of the respective third reset signal line crosses over the second part of the third node portion in the (2k−1)-th column; or
an orthographic projection of the first non-colinear segment on the base substrate partially overlaps with an orthographic projection of the active layer of the driving transistor on the base substrate.
16. The array substrate of claim 14 , wherein, in a (2k)-th column, a second non-colinear segment of the respective third reset signal line crosses over the first part of the third node portion in the (2k)-th column; and
an orthographic projection of the second non-colinear segment on the base substrate is non-overlapping with an orthographic projection of a channel part of the active layer of the driving transistor on the base substrate.
17. An array substrate, comprising:
K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate;
wherein the K number of reset signal lines comprises:
a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤k≤ (K/2); and
a plurality of fourth reset signal lines in (2k)-th columns of the K columns;
wherein the array substrate comprises a plurality of gate lines;
wherein, in a respective pixel driving circuit, a respective gate line comprises a main portion extending along an extension direction of the respective gate line, and a gate protrusion protruding away from the main portion; and
at least 70% of an orthographic projection of the gate protrusion on a base substrate is non-overlapping with an orthographic projection of a reset signal line on the base substrate.