Two transistor gain cell memory with indium gallium zinc oxide
An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.
1. A two-transistor dynamic random access memory (DRAM) cell comprising:
a read bit line;
a write bit line;
a read word line;
a write word line;
a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to the write word line, a first controlled node region coupled to the write bit line, and a second controlled node region; and
a second IGZO transistor with a second gate region, a third controlled node region coupled to the read word line, and a fourth controlled node region coupled to the read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of an integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.
2. The two-transistor DRAM cell of claim 1 , the first and second IGZO transistors comprising n-channel metal-oxide-semiconductor (NMOS) type transistors.
3. The two-transistor DRAM cell of claim 1 , comprising the integrated circuit chip to include a processor, the two-transistor DRAM cell included in a memory array arranged to be an on-die last-level cache for the processor.
4. The two-transistor DRAM cell of claim 3 , the memory array created in the BE metal process stack and the processor created in a front end silicone process stack of the integrated circuit chip.
5. A system comprising:
an integrated circuit chip; and
a two-transistor dynamic random access memory (DRAM) cell that includes:
a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to a write word line, a first controlled node region coupled to a write bit line, and a second controlled node region; and
a second IGZO transistor with a second gate region, a third controlled node region coupled to a read word line, and a fourth controlled node region coupled to a read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of the integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.
6. The system of claim 5 , the first and second IGZO transistors comprising n-channel metal-oxide-semiconductor (NMOS) type transistors.
7. The system of claim 5 , comprising the integrated circuit chip to include a processor, the two-transistor DRAM cell included in a memory array arranged to be an on-die last-level cache for the processor.
8. The system of claim 7 , the memory array created in the BE metal process stack and the processor created in a front end silicone process stack of the integrated circuit chip.